These info are already on AppleDB and OWC etc:
A3143 Mac16,9 Mac Studio M4 Max
A3389 Mac15,14 Mac Studio M3 Ultra
A3240 Mac16,12 MBA 13” M4
A3241 Mac16,13 MBA 15” M4
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M4+ Chip Generation - Speculation Megathread [MERGED]
- Thread starter GoetzPhil
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A3143 Mac16,9 Mac Studio M4 Max
A3389 Mac15,14 Mac Studio M3 Ultra
A3240 Mac16,12 MBA 13” M4
A3241 Mac16,13 MBA 15” M4
Hmmm ... I don't agree on that last part as a blanket statement. It depends on the kind of chiplets - for instance splitting the CPU and GPU dies as Apple is indeed rumored to do for the M5 Pro/Max could allow for chiplet design reuse as AMD does, which AMD claims to reduce costs substantially, or even increased SOC design flexibility.
It's barely better than 6900XT. I understand the value of unified memory, but in terms of raw compute power, Apple's current flagship offering is still lacking.
What if there is an identical core package and identical GPU package? The M5 is a single SoC with one of each, whereas Pro/Max/Ultra have x of each on a package. Kind of like Intels Foveros?
Sure we know. TB5 was *announced* in September 2023. There were no shipping products from any vendor until mid 2024. The M3 shipped in November 2023 (which means chip design was completed MUCH MUCH earlier). That's much too soon to have a working TB5.
All valid points, but not what Apple prioritizes for their Pro and Max chips (which is why I limited my statement to those chips). Their priority is energy efficiency. Going to chiplets will cost them efficiency they're obviously unwilling to give up.
Now, as for the Ultra and hypothetical larger packages - sure, they're already doing (big) chiplets witih the Ultra and I fully expect that to continue.
None of this fixes the efficiency loss. They will be staying monolithic for their laptop chips.
Not likely. That would entail a reset of Apple’s entire approach. In the current generation, you have two tiers, with a distinct divide between them:
[1] A18, A18 Pro, M4
[2] M4 Pro, M4 Max (Brava Chop, Brava)
The structure of the first tier goes all the way back to the A5 and A5X in 2011 and 2012. The second tier started with M1 Pro/Max/Ultra in October 2021 and March 2022.
But I think the idea of “identical” building blocks is interesting. Not counting AMD, which I have read nothing about, both of the known, real-world instances of InFO-LSI pair identical chips (Apple’s 2x Max = Ultra and Nvidia’s Blackwell), so it appears there are distinct advantages to that approach.
So I could see M5 Pro/Max/Ultra with two base components, the GPU and the “core” (everything else) as you call it. Pro and Max would combine them variously on a single SoC, exactly like what was done with M1-M2 Pro/Max. (I’m unsure about the layout of the M3 Pro/Max/Ultra.) For the M5 Ultra, you’d still have the 2x Max version, but an entirely new tier would emerge beyond that, with the two components split out into two building blocks: GPU and Core. InFO-LSI would be used to fuse them into two Ultra+ components, which would then be combined via CoWoS-L packaging in various configurations. I believe Nvidia has an instance of Grace Blackwell that combines four Blackwell GPUs with one Grace CPU.
The base GB200 Superchip with two Blackwells and one Grace is estimated to start at $60,000, so let’s just say that a Mac Pro with one Core and two GPU blocks would be, erm, expensive!
The card would be a self contained Mac. There is no rational reason to constrain it to the space of just MPX ( MP 2019) systems. There is a sizeable number that could be sold to folks who bought a Windows Workstation with an empty slot that still wanted a secondary ( or possible primary ) Mac to use alongside the Windows/Linux box they bought. (e.g., far deep inside the Nvidia GPU moat, but has a subset of macOS programs to run. Could buy a mini and drop on same desk, but neater (less wires ) to put on in the same box. It is the user base looking for containers that Apple has run away. )
MPX purely just for power is goofy. There is a nescient add-in-board power move in the PC land. Not a standard yet but some folks trying options.
If Apple is barely willing to putting UltraFusion on each generation how you are getting to "Extreme"?
The Max as a building block is an overly chunky chiplet. It isn't well grounded chiplet function decompostion. Until Apple fully commits to good chiplet design , the "Extreme" is likely a pipe dream that gets trotted out.
The Mac Studio "Max" version having all appearance of being a non chiplet version is also a very bad omen for any kind of Extreme. The Ultra building block component sitting on 1/2 of Studio , Mac Pro , and some vague cloud server deployment is weak.
All the more so when Apple is off trying to build a Google Tensor clone/replacement.
" ... the report said the new chip contains "many duplicates" of Apple's Neural Engine, so it sounds like it will offer turbocharged performance for AI processing. ...
...
" ... Like Google, Apple is relying on Broadcom for technology to network or link the chips together so they can work in unison to compute data more quickly. ..."
..."
https://www.macrumors.com/2024/12/11/apple-intelligence-servers-new-chip-report/
Another mega big chip for hyper small Mac Pro deployments? Probably not. Even more so when Apple is not charging for Apple Intellingence. Just paying for that Tensor clone has questions marks about paying for it, yet alone another R&D black hole of spending. If US DoJ cuts off that 'free' Billion dollar slush fund from Google each year ... even more so.
The mothership has no major data center.
It is possible that the M3 Max SoC already had TB5 controller but previous devices lacks peripheral TB5 chips (e.g., retimer).
Hmmm ... so looking at Lunar Lake ST CB R24 results from NotebookCheck, the disaggregated design of those chips doesn't appear to have hurt it substantially relative to say the monolithic Strix Point (Halo is chiplets). Now there are caveats here, Lunar Lake is a much smaller chip with on package memory and a slightly better node (N3B vs N4P). So we don't know what LL's efficiency might've been had it been monolithic. That said, the efficiency loss due to multiple chiplets (and indeed a more substantial package with base dies and so forth than Apple's solution) haven't hurt it so bad that it washed away any of those advantages. Further Kuo's M5 Max/Pro prediction is based on Apple adopting one of TSMC's newest packaging technologies which I do not believe has been used so far and thus whose characteristics may not be readily apparent. I'm not saying there will be zero power loss, of course there will be, nor that simply because analyst makes a claim that we should automatically believe them, but I don't think it's crazy to suggest that Apple will adopt chiplets for the Max/Pro die depending on what packaging tech is available and what Apple plans to do with it.
Possible, but unlikely. So far the tea leaves are that 18A itself is facing delays - Kuo is saying that the the signs from supply channels are that Intel isn't gearing up for 18A production to hit its Panther Lake H2 2025 release and its looking increasingly like 2026. Further Intel's statements have gone from claiming to be winding down reliance on TSMC to talking up continued leading edge manufacturing collaboration with TSMC. Then there was the earlier report of Broadcom being unhappy with the early state of yields for 18A (though in fairness almost every node has bad yields during development). Now none of this should be taken as a definite sign of problems and Intel has pushed back against yield issue rumors. But it is looking at least like yield/capacity might be constrained and then there's the issue that Intel needs the capacity to produce their own chips, so what's available to partners to produce will be substantially later - we're talking 2026 or 2027 just for 3rd party 18A shipments. All this is to say when 14A might be available for Apple to produce on is unknown. That said, I wouldn't be shocked if Apple tested the waters at some point to see if Intel is even viable.
Also, to be blunt without trying to get this conversation moved to the political section, the new administration is so vacillating, predicting what the tariffs will be or what exceptions will be granted just a week from now never mind years from now is basically impossible. That chaos alone might make companies reconsider their plans, but it may not depending on how confident they are that they can absorb the risks or get around them.
TBH I'm a little out of it, so I apologize if I'm just repeating what you guys have already said. Kuo's research note on the possible M5 Pro/Max design was very short and boiled down to:
1) Nothing below the Pro would adopt chiplets (so no changes to the base M or A series chips)
2) The M5 Pro/Max would adopt at least a dual die design where the CPU and GPU cores were on separate dies and Apple would adopt one of TSMC's newest packaging technologies (newer than what Apple or Nvidia had used before).
Beyond that we don't know much about the proposed design. Something that would be very similar to what Apple already does in the M4 is a single CPU die for both the Pro and Max CPUs where the Pro CPUs are a heavily binned Max CPU die while it makes two different GPU dies - one Max and one Pro - and swaps them out for different products. You could also imagine two different CPU dies - one Max and one Pro - as well depending on how much they wanted to differentiate Pro and Max (a la the M3 Pro). Most of the "uncore" (IO/memory/display/etc...) would be on the GPU die. Things like the NPU could be on either. They could in theory go with an older node for the GPU or even a third die on an older node for the "uncore" - the latter in particular I don't think is likely yet as that's more of an extrapolation from Kuo's note and jumping to two interconnects would seem to overly complicate Apple's first non-Ultra disaggregated chip (which the Ultra also uses only a single interconnect). That said, it is a possibility (especially for later) depending on Apple's design goals and future TSMC tech. And I believe @leman found Apple patents for mixing and matching dies in 3D packaging.
I'm not saying that this is what Apple will do, but it is a possibility that fits with Kuo's market research (okay glorified tea leaf reading) while also fitting broadly with what Apple's design ethos has been for the Pro/Max chips and only requiring a single interconnect for the Pro/Max chip to keep things simple and "clean" for this (potential) first iteration.
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No. The spec was finalized LONG after the M3 taped out.
If you were Tim Cook would you bet an entire generation (at least) of products on Intel? This seems incredibly unlikely. I'm sure they're keeping their options open, but that probably consists of a test run of something for much smaller products.
It's unclear to me if Intel will have the capacity to supply M6, even assuming 18A and 14A have no further delays or yield issues. I am also skeptical about Apple being willing to do two layouts, one for TSMC and one for Intel - though if Intel's smart (no evidence of this so far) and their process is actually good (also no evidence, either way) they'd subsidize this. The PR value of having Apple do even some of their M6 (or more likely, M7) on Intel would be invaluable.
Sure, eventually this may be true. ISTM that it's unlikely to happen as early as M5 (this year even!), though.
Well, I didn’t know Kuo had said anything about M5 Pro/Max using chiplets, so you’re ahead of me!
As I said, it's very short:
BE Semiconductor Poised to Benefit from iPhone 18 Pro Variable Aperture, Apple PCC/High-End M5â¦
Conclusion: The plummet in BE Semiconductorâs (BESI) stock price in 3Q24 has already priced in the 2H24 shipment delays. Looking ahead toâ¦
This is the part that deals with the M5:
There's precedent - Apple did a gradual switch from Samsung to TSMC by taping out versions of A8 and A9 for both Samsung and TSMC. Did significant production volume with both fabs, too. However, they stopped that and switched to TSMC only from A10 onwards - probably the result of TSMC bringing enough fab capacity online to handle Apple's needs.
But that was a long time ago, and Apple had a fundamentally different motivation - escaping dependence on a major competitor. The technical difficulties of doing dual tapeouts are likely different too. So, I'm hesitant to say that this history has much meaning when trying to predict what Apple is likely to do today.
Yeah maybe M7 i think biggest issue with doing TSMC only is the current administration seems to be very open about high tariffs of any electronics and semiconductor imports, so if TSMC can make chips inside US they'll be ok but otherwise price of iPhones and/or Mac's can grow by ~25-50% and I don't think Arizona fab will produce 2nm anytime soon as they are on 4nm with not enough capacity for new orders.
And I'm pretty sure Apple is not going to sit down and hope for the best assuming Intel 18A is good they would gladly move to Intel Fabs or just buy Intel Fabs (It is for sure better deal for Apple than letting intel get into Qualcomm hands).
You know that the SoC is just one part of the finished product?
Unless 100% of Apple’s products are mined, processed, manufactured and assembled in country, it’s unlikely to escape the tarrifs.
So it looks like inflation will get worst if these tarrifs gets escalated.
Never heard of an A8 tape out for a Samsung node.
There was an A9 on Samsung 14FF LPE and an A9 on TSMC 16FF+.
Apple did that because they were not sure TSMC could pull 16FF+ fast enough into HVM.
It had nothing to do with a gradual switch from Samsung to TSMC.
You know we are talking about most important part?
There are also multiple companies and countries who can do all of the above, but 2nm semiconductors there is only TSMC (in Taiwan atm) and maybe Intel who is only one doing this in US (thats why both NV and Qualcomm are rumored to use 18A, there were even rumors about Qualcomm buying Intel fabs).
SoIC appears to integrate “holistically” into TSMC’s existing, evolving structure of InFO and CoWoS. Apple can still use the 2x Max = Ultra formula, as well as going beyond it into the next-step CoWoS for PCC/Mac Pro I’ve been suggesting. This welcome news doesn’t take anything off the table. See the third/final graphic here (I’m not sure, but I think the old “-X” in the title is a variable, and not specific, so it includes SoIC-mH):BE Semiconductor Poised to Benefit from iPhone 18 Pro Variable Aperture, Apple PCC/High-End M5â¦
Conclusion: The plummet in BE Semiconductorâs (BESI) stock price in 3Q24 has already priced in the 2H24 shipment delays. Looking ahead toâ¦medium.com
I also love the more recent “Whats, Whys, and Hows” overview. Especially the rocket ship versus automobile versus bicycle graphic. It’s friendly and fun, but also unequivocal in a way that I think Apple’s current marketing could probably learn from. I’m always suspicious when somebody insists, “I know what I’m doing” — people who actually know what they’re doing don’t need to say that — that’s often a red flag, in my experience, but this says it without saying it, if you know what I mean:
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Yeah I wasn't trying to suggest that it takes anything off the table - the notion I was trying to get across is that a connector for two or more dies could expand to the Pro and Max lines in addition to the Ultra and then give my own thoughts as to how that might work for the Pro/Max. However, I should say that, beyond noting that this way of packaging dies is new, Kuo doesn't really give any particular reason in this note why he believes that Apple will adopt the ultra fusion connector for the M5 Pro/Max. Which is why though he may have additional information that he isn't sharing, I don't think we should take as a guarantee his prediction that Apple will adopt SoIC bonding for dual+dies for the upcoming Pro/Max (even if they adopt it for the Ultra). I also don't think we should dismiss that Apple might adopt chiplets for the Pro/Max in the M5 generation either. Rather, my own view is that it is something that could plausibly happen in the near future, including the M5.
I can find absolutely nothing I consider trustworthy about SoIC-mH, but the name SUGGESTS something like the Apple packaging patents I referred to when the M1 Ultra first came out, like https://patents.google.com/patent/US20180294230A1
The idea of these patents is we first create, dice, and test chiplets (equivalent of a Max chip) then when place the known good ones side by side to form an "artificial wafer" held together by molding compound. This artificial wafer is sent though the fab BEOL to lay down additional wiring between the chiplets (ie to create the Fusion bridge between two Maxs).
This technology was obviously not used for M1 and M2 (both use something like EMIB) and it seems likely the same is true for M3. But maybe it was just ten years ahead of its time, an idea that Apple proposed to TSMC and they've been perfecting for ten years?
If you can get this to work, you have a path to "fairly easily" creating substantially larger packages because once you have built the artificial wafer as you like, you can slap down connections wherever you want.
Scroll down this page https://news.futunn.com/en/post/481...xpansion?level=1&data_ticket=1741464782805886 till you get to the picture, which looks a whole lot like the Apple patent pictures, and describes the massive jump in size available for the newest version of CoWoS, from 3.5x reticle to 40x reticle!
Both elements suggest that the Apple patent of 2017 is coming to production.
Building on this,
US20190319626A1 - Systems and methods for implementing a scalable system - Google Patents
Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.
patents.google.com
I suspect the Extreme (and successors: the Colossal?, the Juggernaut?, the Terminator?) are on their way, we all just underestimated how long innovations in the physical space (ie packaging) as opposed to in the logical space (new microarchitectures and protocols) take...
If Apple implements TSMC's 2.5D SoIC-mH for the M5 Max on N3P, would be enough area over the GPUs for the SDRAM to be stacked vertically over them (potentially reducing power consumption by 25-40%)?
If sales of the Macbook Pro M5 Max are an Apple priority (compared with the Mac Studio or Mac Pro), and Apple seeks brand leadership (with Samsungs Elite laptops chomping on its heals) - how much of a jump in performance do we think Apple will be aiming for?
With the M4 Max already audibly ramping up fans under load - and switching to N3P only saves 10% power (or allows 10% more GPU cores for the same load) - perhaps Apple will have to jump to TSMC's 2.5D SoIC-mH just to benefit from reduced power utilisation (and be able to offer a more formidable high end Laptop)?
If Apple deems a 10% faster M5 Max to be insufficient - perhaps an SoIC-mH M5 Max could give >=25% jump in performance later this year (compared to the M4 Max)?.
If the Mac Studio M3 Ultra is around 8% faster (muticore) than the M4 Max (TechRadar) - I imagine an M5 Max Macbook Pro will outperform Apple's top end Studio M3 Ultra in many real world cases (that don't scale well), with the M3 Ultra only performing 10% faster for GPU intensive loads.
With a comparable price of the Mac Studio M2U and Macbook M4 Max - Apple likely needed to release a Stop-Gap offering (M3 Ultra) in 2025 Q1 - to keep Studio users from defecting to Laptops. IF Apple offered the same stop-gap (M3 Ultra) measure next week - many a Pro user that had ponied up >$7000 only for the 2025 Q4 M5 Max Macbook to outperform at close to half the price would be up an arms; And if Apple then offered the M5 Ultra in 2025 Q3/Q4 (likely before the Macbook) - Pro users would be pissed that had upgraded 6 months early.
If Apple have a supply of M5 Ultra Chips ready for the Mac Pro this year - why wouldn't they also offer this as an Additional upgrade tier in the Mac Studio for a price that is between the M3 Ultra Studio and the base price of the Mac Pro M5 Ultra? Say $1000 less than the Mac Pro?
If Apple don't also offer the M5 Ultra in the Mac Studio in 2025 ... It will likely result in customers Waiting until Apple release the Studio with M5 before they buy .. or, for many to consider switching from last-in-line desktops with two generation old architecture technology to the yearly state of the art Macbooks (with Max chips) that Apple releases like clock work in Q4 each year.
Well, the above could allow for a substantial boost in GPU processing power with Apple Silicon; I can imagine four 16-core CPU+ chips coupled with 12 GPU+ chips, supporting 4TB of memory with 8TB/s of UMA bandwidth...! ;^p