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M4+ Chip Generation - Speculation Megathread [MERGED]
- Thread starter GoetzPhil
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No, it’s not the new nm. It’s actually 0’1nm. 10Å=1nm
I do wish TSMC would have used Å (instead of A) but I understand why not. The Wikipedia page @casperes1996 provided above says it all.
It does have the potential to save on ink!
Wrong analysis in so many ways.
1. Everyone knew that A16 is N2P with SPR, this is no surprise, and there is no "only" about it. SPR is a big deal.
2. Thermal issues are a problem for the sort of chips that AMD and nVidia sell, they are much less of an issue for Apple.
3. Apple is specifically working on designs that are aware of the thermal characteristics of BSPDN, eg
https://patents.google.com/patent/US20250112154A1
4. BSPDN provides multiple benefits beyond just the reduced voltages that Intel talks about. In particular SPR also provides for reduction of wiring clutter. (Intel does not talk about this because, like the idiots that they always are, they cared more about being FRIST!!! than being best, and adopted a technology that's simpler than TSMC's -- but that also has much less potential for alleviating wiring clutter.)
Again Apple is already designing circuits to take advantage of this, eg this SRAM:
https://patents.google.com/patent/US20230299068A1
As you should know, SRAM scaling has halted for the past few rounds of process improvement, mainly because of wiring clutter. Alleviating that allows SRAM scaling to resume.
None of this gives me any insight into timing, and timing is always a complex mixture of confidence, cost, and competition. But IMHO if Apple has a choice between N2P and A16 being available in time, A16 will be chosen; it's imply a much better fit to what Apple wants from a process.
Thanks!
On timing, it seems like it will have to be a gradual transition, even if everything is on schedule. The first 1.4nm/14Å generation (A14) will not have SPR [TSMC unveils 1.4nm technology], so there will be a two-year gap between first-generation SPR (A16) and second-generation SPR (A14P?). So if Apple keeps up the current annual cadence for the A-series and the base M with Pro/Max, then maybe the roadmap could look like this:
A19/A19 Pro (September 2025) [TSMC 3nm gen3 "N3P"]
M5 (October 2025) [N3P]
M5 Pro/Max (October 2025) [N3P]
M5 Ultra (March 2026) [N3P]
A20/A20 Pro (September 2026) [TSMC 2nm gen1 "N2"]
M6 (October 2026) [N2]
M6 Pro/Max (October 2026) [N2]
A21/A21 Pro (September 2027) [TSMC 2nm gen2a "N2P"]
M7 (October 2027) [N2P]
M7 Pro/Max (October 2027) [N2P]
M7 Ultra (March 2028) [TSMC 2nm gen2b "A16"]
A22/A22 Pro (September 2028) [TSMC 14Å gen1 "A14"]
M8 (October 2028) [A14]
M8 Pro/Max (October 2028) [A14]
A23/A23 Pro (September 2029) [TSMC 14Å gen2 "A14P?"]
M9 (October 2029) [A14P?]
M9 Pro/Max (October 2029) [A14P?]
M9 Ultra (March 2030) [A14P?]
NOTE: The above uses standard M1-to-M4 silicon names and release dates/cadences. I recognize that M5+ and the (rumored) introduction of SoIC could and likely will change this structure, but I see little point in trying to guess about that, or about which products might get the M2 MBA or M4 IPP early-launch halo. We may know more in less than two weeks...
I think we’re eventually move to photonics instead of endlessly pursuing shrinking silicon (because as you note, there’s a limit).
It will sacrifice size for speed and I think we’re going to wind up in a pseudo FPGA photonic world in 25 years.
The names aren't really connected to the transistor size anymore. If you want to give the foundries the benefit of the doubt, one could say it's a relative measure of the overall logic transistor density compared to when the "nm" did correspond to transistor size. I can't remember when the last time "nm" name actually corresponded to anything relevant about transistor size, but let's say for TMSC it was 20nm. Thus the name TSMC N2 implies you can (in theory) fit 10x as many TSMC N2 GAA transistors in the same area as you could fit TSMC 20nm planar transistors, but the transistors themselves aren't actually 1/10th the size.
Replacing silicon with other materials is an active area of research and we've got several candidates that are clearly better, but it's a matter of being able to produce them at the same volume as silicon. There's an entrenched market advantage to silicon that any new material will have to overcome to get adopted.
As others mentioned, the fab's process node numbers are more for marketing. The actually sizes of gate components are much larger.
According to wikipedia, TSMC's 1nm node has a metal pitch size of 16nm.
A diagram of a logic gate.
High NA lithography EUV from ASML will give more room for node shrinkage. TSMC doesn't need it for its 1.4nm node yet.
Other Materials dont allow for smaller structures but for higher frequencies due to higher charge mobilities leading to lower resistance, less voltage drops and less heat production. Also the thermal resistance can be lower causing better heat dissipation.
Gallium Arsenide is "the material of the future, and always will be". The mobility is great, but reality has shown that it's just too difficult to work with as a logic material. RCA tried, but couldn't make it viable (even with DoD help). Cray tried, for the Cray-3, and it bankrupted the company.
And GaAs has worse thermal resistance than Si.
The other (possible) contenders, like SiC or GaN again have various practical limitations. SiC might get off the ground as a logic material for simple logic to operate in very hot environments (think eg controllers in engines).
Problem is so much money has been poured over 70 years into understanding and solving every minor aspect of Si, and no-one wants to replicate all that knowledge, especially if you don't even know that it can be done -- maybe some of the handling problems simply are insoluble?
The most like way this will play out to "other materials" is the transition to 2D materials, forming the transistor switching guts, but placed on an Si scaffold. And no-one, honestly, knows if that is actually viable up to the scales and complexity required to replace Si. We'll see...
If SMIC (China) create a 7nm (40nm Metal pitch) 3D-IC with 4 layers of 4 x 4 CPU - how would it ‘stack up’ against a TSMC N3 chip with a single plane of transistors (with a 8 x 8 CPU cluster)? Would the roughly half the maximum distance between two CPUs result in chip with half the latency?
Would IMEC need to rewrite their nodes definitions to cater for SMIC introducing 3D-ICs to older process nodes?
Uncle Sam is busy halting exports of 3D IC routing software Eastwards - to impede 3D IC progress I presume … but with 1/2 of the AI researchers in China - is that really going to slow them down?
Will their dearth of EUV tools - also cause them to invest in carbon nanotubes sooner:
- a material that could increase electron mobility
- could greatly reduce resistance as the atomic scale
- be used like (high efficacy) diamond to rapidly dissipate heat through a spiders web of thermal via out to the 3D external surface of the 3D-IC package (so that the 100 deg C junction temp can be cooled down at a far higher rate)
The Next Platform : Three-Way Race to 3D-ICs
Would IMEC need to rewrite their nodes definitions to cater for SMIC introducing 3D-ICs to older process nodes?
Uncle Sam is busy halting exports of 3D IC routing software Eastwards - to impede 3D IC progress I presume … but with 1/2 of the AI researchers in China - is that really going to slow them down?
Will their dearth of EUV tools - also cause them to invest in carbon nanotubes sooner:
- a material that could increase electron mobility
- could greatly reduce resistance as the atomic scale
- be used like (high efficacy) diamond to rapidly dissipate heat through a spiders web of thermal via out to the 3D external surface of the 3D-IC package (so that the 100 deg C junction temp can be cooled down at a far higher rate)
The Next Platform : Three-Way Race to 3D-ICs
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Any guesses on the codenames of upcoming chips?
source: https://asahilinux.org/docs/hw/soc/soc-codenames/#socs
"C" in "Sotra_C" seems to stand for "chop", "S" for "single", and "D" for "dual". The rest of them are my pure speculations.
source: https://asahilinux.org/docs/hw/soc/soc-codenames/#socs
| Marketing | Internal | Codename | SoC | P-Core | E-Core |
| M3 Pro | H15J | Lobos | T6030 | Everest | Sawtooth |
| M3 Max | H15J/H15S | Palma | T6031 / T6034 | Everest | Sawtooth |
| M4 | H16G | Donan | T8132 | ||
| M4 Pro | H16S | Brava Chop | T6040 | ||
| M4 Max | H16C | Brava | T6041 | ||
| A18 | H17A | Tupai | T8140a | ||
| A18 Pro | H17P | Tahiti | T8140 | ||
| M5? | Hidra | ||||
| M5 Pro? | Sotra_C | ||||
| M5 Max? | Sotra_S | ||||
| M5 Ultra? | Sotra_D | ||||
| A19? | Thera | ||||
| M6? | Komodo | ||||
| A19 Pro? | Tilos |
"C" in "Sotra_C" seems to stand for "chop", "S" for "single", and "D" for "dual". The rest of them are my pure speculations.
The original leak says Komodo is M6 and Borneo is M7. Sotra is not specified, so it could be M5 Pro/Max/Ultra like you surmise. Baltra is thought to be the M7 data center silicon.
Hidra, however, is Mac Pro. That leak was dead-on with regard to the Mac Studio, so I think we should assume it’s accurate. Here’s what I wrote about this in the WWDC 25 what-to-expect thread:
… We know Apple planned to launch an M5 Mac before October: Mac17,1 and Mac17,2. There are only two remaining possibilities for those identifiers: Mac Pro and/or iMac+.
If Hidra is M3 Ultra/Extreme, then the two M5 identifiers can’t be Mac Pro. So that just leaves iMac+. However, if Hidra is the first generation of a new class of Apple silicon (with Baltra as its second generation), then it could be Mac Pro. Even if not announced next week, but later on.
I’m thinking a Summer launch event, featuring Mac Pro, Pro Display, and, most importantly, the Private Cloud Compute data center(s), thereby launching the privacy-focused aspects of Apple Intelligence that were featured last year at WWDC. iPhone 16 would get them a month or two before iPhone 17 is launched.
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You can control your mac cursor with your head and click by blinking. That feature is there in the mac accessibility settings for years.
We know M3 Ultra is two M3 Max chips fused, so its codename must be Palma 2C or something similar.
I still believe Hidra is more likely to be M5 than Mac Pro class chip like "M3 Extreme". Here is my reasoning:
- Based on the chip development cycle, M5 codename must have been leaked and it has to be one of the names listed above.
- I think Thera and Tilos are A19 and A19 Pro, not M5. Because they follow the same pattern as the previous generation:
- Tupai (A18) and Tahiti (A18 Pro) are islands in French Polynesia
- Thera and Tilos are Greek islands in the Aegean Sea
- This leaves us only with Hidra as M5. Hidra and Sotra are islands in Norway. Again that makes sense.
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~
If Hidra ≠ Mac Pro, then sure. It’s possible a Mac with M5 prototypes in it was being tested at that point (April 2024). They are all island names (even Jade, an island in Taiwan) and it’s a mistake to read anything into Hidra (a Norwegian island), like many people have done, even going so far as to spell it “Hydra.” They are selected at random from a list, the whole point of a codename is to not convey any information in it.
Well, for one, it could be Sotra. M5 may not be structured like M1-M4, and your interpretations (which make sense) of the _C, _S, and _D suffixes may not be accurate, especially given how S is used elsewhere in that chart, also C.
If Hidra ≠ Mac Pro, then sure. It’s possible a Mac with M5 prototypes in it was being tested at that point (April 2024). They are all island names (even Jade, an island in Taiwan) and it’s a mistake to read anything into Hidra (a Norwegian island), like many people have done, even going so far as to spell it “Hydra.” They are selected at random from a list, the whole point of a codename is to not convey any information in it.
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Sorry, I started responding before your edit hit. MR doesn’t notify when edits take place, only new posts.
I knew about the Norway connection, but I still think it’s iffy to assume we know why two obscure Norwegian islands were chosen from the list around the same time, it could be that Hidra is related to Sotra in some other way. They could share an approach to advanced packaging, for example. We know there are big changes coming soon in that respect.
Actually, you might be right. C is more likely to be Max and S to be "chop". H14C is Rhodes 1C (M2 Max) and H14S is Rhodes Chop (M2 Pro); H16S is Brava Chop (M4 Pro) and H16C is Brava (M4 Max).
In macOS 15.5 headers (/Library/Developer/CommandLineTools/SDKs/MacOSX15.5.sdk/System/Library/Frameworks/Kernel.framework/Versions/A/Headers/cpuid.h), M4 Pro (H16S) is called Brava S and M4 Max (H16C) is called Brava C.
Sotra_S and Sotra_C then are very likely to be M5 Pro and M5 Max.
But as you said, M5 could well be Sotra_D and M5 Ultra be Hidra, or the other way around.
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Totally agree that the codename could be random. In fact, the past codenames within the same generations are not always related. Sometimes they are, like in M2 and M3 generations: Ibiza, Lobos, Palma are in Spain; Ellis, Staten, Rhodes are in the US. But in M4 generation Donan and Brava are not related.