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tenthousandthings

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May 14, 2012
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My thoughts about M4+ center around TSMC's approach to the requisite architectural transition the semiconductor industry is currently implementing. The competition has undertaken some or all of these major advances together: 3nm-class die shrink, gate-all-around (GAAFET) transistors, and backside power delivery network (BPDN or BSPDN): Samsung with both SF3 and Multi Bridge Channel FET, and Intel with both RibbonFET and PowerVia. TSMC, by contrast, is spreading that out over four (five if you count N3) generations: N3E (3nm), N3P (optical shrink), N2 (GAAFET), N2P (BSPDN). This cautious approach may be the result of lessons learned during the bumpy FinFET transition ca. 2015 (A9 and A9X).

Also, I seem to be in a minority, but I believe Apple will skip N3E and leapfrog from N3 to N3P for M4 (June 2025). Apple's apparent 18-month M-series cadence, however, means A20 and M5 will be on N2P, so both GAAFET and BSPDN will be incorporated into the M-series at the same time, in October 2026.

SRAM is not scaling anymore (at least not for several more years. ) N3E goes BACKWARD from N3 to N5 sizes.
Pouring on SRAM like ketchup isn't a viable path right now.

I'm not in a position to disagree, but, according to Anandtech, SRAM density will benefit from N3P's overall optical shrink (adjustments to the optical performance of the scanners), so, if I'm right about the process node, perhaps its role could be increased in the M4 GPU designs?
 
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High IQ Person

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Dec 31, 2022
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My thoughts about M4+ center around TSMC's approach to the requisite architectural transition the semiconductor industry is currently implementing. The competition has undertaken some or all of these major advances together: 3nm-class die shrink, gate-all-around (GAAFET) transistors, and backside power delivery network (BPDN or BSPDN): Samsung with both SF3 and Multi Bridge Channel FET, and Intel with both RibbonFET and PowerVia. TSMC, by contrast, is spreading that out over four (five if you count N3) generations: N3E (3nm), N3P (optical shrink), N2 (GAAFET), N2P (BSPDN). This cautious approach may be the result of lessons learned during the bumpy FinFET transition ca. 2015 (A9 and A9X).

Also, I seem to be in a minority, but I believe Apple will skip N3E and leapfrog from N3 to N3P for M4 (June 2025). Apple's apparent 18-month M-series cadence, however, means A20 and M5 will be on N2P, so both GAAFET and BSPDN will be incorporated into the M-series at the same time, in October 2026.



I'm not in a position to disagree, but, according to Anandtech, SRAM density will benefit from N3P's overall optical shrink (adjustments to the optical performance of the scanners), so, if I'm right about the process node, perhaps its role could be increased in the M4 GPU designs?
Would be funny if TSMC gets stuck and Apple silicon stagnates. What will the Apple fans say when they see no performance or efficiency gains for 5 years straight? Will they finally wake up and realize that Apple's "design" is worthless marketing gimmick and only lithography matters for chip performance?
 

quarkysg

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Would be funny if TSMC gets stuck and Apple silicon stagnates. What will the Apple fans say when they see no performance or efficiency gains for 5 years straight? Will they finally wake up and realize that Apple's "design" is worthless marketing gimmick and only lithography matters for chip performance?
I suppose you are also of the opinion that you can produce the best furniture in the world when you are given the best tools? Skills and experience is not important at all, am I right?
 
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High IQ Person

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I suppose you are also of the opinion that you can produce the best furniture in the world when you are given the best tools? Skills and experience is not important at all, am I right?
Poor analogy. A much more apt analogy would involve a customer ordering pizza from dominos. There is no trade secret or “skill” with chip design just like there’s no skill in “designing” a pizza from dominos. Whatever pizza you tell dominos to make can be easily made by someone else if they wanted to. Likewise in chip development, the hardest part is the manufacturing process, as that determines the yield curve. Apple just has to decide how much money they want to spend and where in the yield curve they want to be. The performance profile can be easily matched by anyone if they wanted. Your large pepperoni pizza from dominos isn’t special. I could’ve done the same thing.


What Apple brings to the table is economies of scale through their large sales volume. They’re not bringing much technical expertise, if at all. It doesn’t take any skill whatsoever to determine how large you can make your core, how many you can fit in the SoC and what clock speed they can run at. These are incredibly elementary tasks that a 3rd grader can do. The primary limitation is the manufacturing process.
 
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Carrotstick

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Would be funny if TSMC gets stuck and Apple silicon stagnates. What will the Apple fans say when they see no performance or efficiency gains for 5 years straight? Will they finally wake up and realize that Apple's "design" is worthless marketing gimmick and only lithography matters for chip performance?
Design matters look at A16 vs Snapdragon 8 Gen 2. Same node but the A16 had much better CPU performance and efficiency wise.
 

senttoschool

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Also, I seem to be in a minority, but I believe Apple will skip N3E and leapfrog from N3 to N3P for M4 (June 2025). Apple's apparent 18-month M-series cadence, however, means A20 and M5 will be on N2P, so both GAAFET and BSPDN will be incorporated into the M-series at the same time, in October 2026.
I think there is a low chance of this happening. N3E will be used for A18 Pro. Therefore, it'd be easier to build the M chips on the same node as A18 Pro.

Also, it's not apparent that there is an 18-month cadence. In fact, M3 Pro/Max came out only 10 months after M2 Pro/Max. I'm not suggesting that Apple has a 10 month cadence. Occam's Razor suggests it's a 12 month cadence that follows the iPhone cadence since they both use the same architecture and occasionally, this cadence will deviate due to supply issues, node timings, pandemics.
 

senttoschool

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Would be funny if TSMC gets stuck and Apple silicon stagnates. What will the Apple fans say when they see no performance or efficiency gains for 5 years straight? Will they finally wake up and realize that Apple's "design" is worthless marketing gimmick and only lithography matters for chip performance?
So what. If TSMC gets stuck, the world has bigger problems than Apple Silicon Mac chips. Nearly every industry on Earth have dependency on higher computing power in order to make efficiency gains - whether it's directly running applications or using ever more powerful chips to run simulations/studies.
 
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High IQ Person

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Design matters look at A16 vs Snapdragon 8 Gen 2. Same node but the A16 had much better CPU performance and efficiency wise.
Wrong. A16 was on N4P while SD8G2 was on N4. You’d need to look ant Gen 3 to have a more even comparison. Also, QC went with smaller cores to make room for their superior GPU while Apple went with larger CPU cores and limited GPU die space. These are design choices. It’s like designing a pizza. Whatever you design I can easily replicate. It’s not a trade secret.
 

High IQ Person

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Dec 31, 2022
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So what. If TSMC gets stuck, the world has bigger problems than Apple Silicon Mac chips. Nearly every industry on Earth have dependency on higher computing power in order to make efficiency gains - whether it's directly running applications or using ever more powerful chips to run simulations/studies.
In that case, hopefully Intel or Samsung breaks through, but there will be a period where Apple can’t move to another foundry due to capacity issues with these 2. It will be funny seeing Apple fans twist themselves into a pretzel trying to explain why everyone using Intel/Samsung foundry is improving while Apple is stagnating.

Regardless, my point still stands that Apple’s “design” is a marketing gimmick. There’s nothing special or hard about it. It’s as hard as designing a pizza from dominos.
 
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Carrotstick

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Wrong. A16 was on N4P while SD8G2 was on N4. You’d need to look ant Gen 3 to have a more even comparison. Also, QC went with smaller cores to make room for their superior GPU while Apple went with larger CPU cores and limited GPU die space. These are design choices. It’s like designing a pizza. Whatever you design I can easily replicate. It’s not a trade secret.
It is trade secret ARM nor Qualcomm can’t copy Apple CPU designs.
 
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quarkysg

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Poor analogy. A much more apt analogy would involve a customer ordering pizza from dominos. There is no trade secret or “skill” with chip design just like there’s no skill in “designing” a pizza from dominos. Whatever pizza you tell dominos to make can be easily made by someone else if they wanted to. Likewise in chip development, the hardest part is the manufacturing process, as that determines the yield curve. Apple just has to decide how much money they want to spend and where in the yield curve they want to be. The performance profile can be easily matched by anyone if they wanted. Your large pepperoni pizza from dominos isn’t special. I could’ve done the same thing.


What Apple brings to the table is economies of scale through their large sales volume. They’re not bringing much technical expertise, if at all. It doesn’t take any skill whatsoever to determine how large you can make your core, how many you can fit in the SoC and what clock speed they can run at. These are incredibly elementary tasks that a 3rd grader can do. The primary limitation is the manufacturing process.
Wow, you seem to know a lot when it come to CPU architecture design. You must have designed many a wonderful CPU products.

Equating CPU micro-architecture design to baking pizza ... hmm ... I wonder how many in this world knows how to bake a pizza compared to one that can design and produce a high performance CPU micro-architecture. I guess to you, every problem is a nail when you're wielding a hammer.

What's this about poor analogy ??? ...
 
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casperes1996

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In that case, hopefully Intel or Samsung breaks through, but there will be a period where Apple can’t move to another foundry due to capacity issues with these 2. It will be funny seeing Apple fans twist themselves into a pretzel trying to explain why everyone using Intel/Samsung foundry is improving while Apple is stagnating.

Regardless, my point still stands that Apple’s “design” is a marketing gimmick. There’s nothing special or hard about it. It’s as hard as designing a pizza from dominos.
For years intel had a tick-tock update cycle where every second year would be a new node and every other would be a new design. Some of the biggest performance wins from that time was with new designs on existing nodes.

Apple does not use standard ARM cores. They pay the highest licensing price for the right to design their own cores and there’s a reason for that. Competitive advantage. If that didn’t matter they’d just use standard arm cores.
 

High IQ Person

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Dec 31, 2022
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For years intel had a tick-tock update cycle where every second year would be a new node and every other would be a new design. Some of the biggest performance wins from that time was with new designs on existing nodes.

Apple does not use standard ARM cores. They pay the highest licensing price for the right to design their own cores and there’s a reason for that. Competitive advantage. If that didn’t matter they’d just use standard arm cores.
And on 14nm++++++++++++++++?

Apple designs their own cores for marketing, not because they can do it better. See how many people got brainwashed into thinking “designing” a pizza from dominos was impressive? It actually worked. It’s a marketing stunt.
 

High IQ Person

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Dec 31, 2022
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Wow, you seem to know a lot when it come to CPU architecture design. You must have designed many a wonderful CPU products.

Equating CPU micro-architecture design to baking pizza ... hmm ... I wonder how many in this world knows how to bake a pizza compared to one that can design and produce a high performance CPU micro-architecture. I guess to you, every problem is a nail when you're wielding a hammer.

What's this about poor analogy ??? ...
I actually have but will not say to jeopardize my anonymity. Designing CPU is child’s play and can be done by any average 10-year-old in a day’s training. It really is like ordering pizza.

There is no trade secret.
 
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quarkysg

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I actually have but will not say to jeopardize my anonymity. Designing CPU is child’s play and can be done by any average 10-year-old in a day’s training. It really is like ordering pizza.

There is no trade secret.
If you say so.

Btw, your pizza is good because you have good oven amirite?? No no … must the be premium wood you‘re using. Nothing to do with your understanding and experience in baking pizza … amirite?? Any 10 year on can do it amirite??

Sorry … can’t help myself.
 

High IQ Person

macrumors regular
Dec 31, 2022
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If you say so.

Btw, your pizza is good because you have good oven amirite?? No no … must the be premium wood you‘re using. Nothing to do with your understanding and experience in baking pizza … amirite?? Any 10 year on can do it amirite??

Sorry … can’t help myself.
Completely inaccurate.
The components of the pizza shop like the oven are supplied by external companies like how the EUV machines are supplied by ASML.

The fab is the baker with the trade secret that determines the taste, how big they can make the pizza, what toppings are available, etc.

The designer brings business to the pizza shop by finding customers. They don’t have any trade secrets. They can control what size they want the pizza and what toppings they want to add to the pizza (Think of an SoC and the limited amount of space on the die). You can’t just add every topping you want due to space issues and yield. Again, there is no trade secret.

the designer’s primary goal would be finding out which topping their customers want and asking the pizza shop to make them.
 

Appletoni

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And on 14nm++++++++++++++++?

Apple designs their own cores for marketing, not because they can do it better. See how many people got brainwashed into thinking “designing” a pizza from dominos was impressive? It actually worked. It’s a marketing stunt.
That's wrong:
Look at:

The developers have done the work, tuning, optimizations on:
-Cortex-X1
-Cortex-A76
= These are not Apple ARM CPUs.

Now look at the speed ups.

Now compare with Apple ARM cores +75.63% speed up.

Now take a look here and do a Stockfish 14.1 benchmark: https://forums.macrumors.com/thread...24.2398264/page-2?post=33035191#post-33035191
 

tenthousandthings

Contributor
May 14, 2012
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320
New Haven, CT
I think there is a low chance of this happening. N3E will be used for A18 Pro. Therefore, it'd be easier to build the M chips on the same node as A18 Pro.

Also, it's not apparent that there is an 18-month cadence. In fact, M3 Pro/Max came out only 10 months after M2 Pro/Max. I'm not suggesting that Apple has a 10 month cadence. Occam's Razor suggests it's a 12 month cadence that follows the iPhone cadence since they both use the same architecture and occasionally, this cadence will deviate due to supply issues, node timings, pandemics.
Sorry, I should have made it clear that I think A18 will also be on N3P. So I agree A18/M4. TSMC is saying "2H 2024" for N3P high-volume production, which is identical to what they said for N4P (A16) and N3 (A17/M3). To my mind, it's virtually certain that A18 will be on N3P. Apple and the iPhone will once again be the first consumer product on the new node. This has been happening for almost a decade now (since A8/A8X in 2014), it's not hard to see coming. N3E is the exception, not the rule.

As for Occam's Razor, I'll admit it is too early to make assumptions, but this is the speculation thread, after all! I'd suggest the simplest explanation is that Apple's roadmap always had the Mx and Mx Pro/Max coming out at the same time (i.e., within a month of one another). This pattern also goes all the way back to the early days of Apple Silicon, with the A6/A6X in 2012. A14/M1 also fits. There is only one exception (other than A15/M2), the A10/A10X, but that involved a process node change (with the A10X iPad Pro being the first consumer devices on TSMC 10nm), the only time that (switching process nodes midstream) has happened. So most likely the gap between M1 and M1 Pro/Max was on the roadmap for the transition before the pandemic, while the gap between M2 and M2 Pro/Max was not.

Regardless, more than a decade of Apple silicon history argues that the M3 and M3 Pro/Max launching at the same time is likely to be the rule going forward. So that explains your 10-month Pro/Max course correction, putting the M-series launch cadence back on track (after it went off-track for M2). Mx and Mx Pro/Max will come out at the same time as long as Apple continues to use monolithic dies, I'll guess wildly that will be until about 2030, when heterolithic integration seems (to me) inevitable, resulting in changes to the architectural (and, yes, marketing) approach. That's probably the biggest, most closely-held of trade secrets, when and how Apple plans to make that jump. It's also the biggest unknown in terms of science and innovation, there are challenges looming at "1nm" and beyond, not just for TSMC, but for everyone.

So, Occam's Razor suggests that the A15/M2 pattern is what will happen for A18/M4. That is the simplest explanation. The A18 will launch on N3P in September 2024, and the M4 will launch in June 2025, also on N3P. The only difference with regard to the A15/M2 timeline is that the M4 Pro/Max will launch alongside the M4 at WWDC 2025.
 
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tenthousandthings

Contributor
May 14, 2012
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New Haven, CT
Is there a reason ‘High IQ Person’ is being replied to seriously? They’re clearly unserious.
Plus, the thing they find "funny" (TSMC hitting science and innovation roadblocks) is actually happening with regard to Samsung and Intel's attempts to integrate the three industry-wide initiatives I mentioned. Samsung announced production of its groundbreaking 3nm die shrink SF3E with GAAFET in June 2022, but somehow it still isn't in their flagship 2024 Galaxy phones. Intel rightfully trumpets their PowerVia (backside power rail) implementation, but they are demonstrating it on Intel 4 (formerly known as Intel 7). It won't make it into the real world until their "20A" (2nm) die shrink goes into production later this year, and then into consumer products in 2025? So suddenly their two-year head start on backside power becomes one year, and TSMC's experience allows A20/M5 on N2P in September/October 2026 to erase that edge entirely.

Don't get me wrong, unlike that "Person," I want to see Samsung, Intel, and TSMC all succeed. I don't think what they are hoping for is funny. Rising tide lifts all boats. I think Intel is doing okay, they have different marketing priorities from Apple, so they do the ambitious roadmaps to generate interest (I think Apple could learn from that), but all signs are that they are actually NOT trying to do everything at once like they did in the past, which got them into trouble. They talk big but in fact they are rolling out the three elements I mentioned almost as cautiously as TSMC is, reducing the odds of stepping on a scientific rake like they have in the past.
 
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MayaUser

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Nov 22, 2021
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And on 14nm++++++++++++++++?

Apple designs their own cores for marketing, not because they can do it better. See how many people got brainwashed into thinking “designing” a pizza from dominos was impressive? It actually worked. It’s a marketing stunt.
"High IQ person" you are wrong, you cannot even prove what are you saying because its mathematically wrong
 
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Tagbert

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Would be funny if TSMC gets stuck and Apple silicon stagnates. What will the Apple fans say when they see no performance or efficiency gains for 5 years straight? Will they finally wake up and realize that Apple's "design" is worthless marketing gimmick and only lithography matters for chip performance?
If that reductionist view were true, then you wouldn’t see such great performance of Apple iPhone chips for over a decade when Qualcomm chips have been produced on the same process nodes in most cases.

Apple does have talented chip designers/engineers and processes. They also can tune their chips to match the needs of the OS and apps running on those chips. Fabbing on a smaller process node is just one more reason Apple’s chips are very good.
 
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