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Apple uses Xeon processors since Mac Pro 1,1. All other releases do not matter. E5's are not on market yet. All premature death certificates are useless. It is not a matter of waiting for Apple, it is a matter of listening to end users who "think" they know what they are talking about. If the Pro dies it will be officially disclosed. I'll even sign that death cert if they fail to deliver updates after 1-2 months of E5 launch. Mac Pro's will be updated when proper (see above) parts are on market. Or they will change up the form factor and offer some kind of hybrid thing. The processors they have avoided upgrading to made no fiscal sense for them. Couple MHz clock bumps to existing architecture to destroy your profit margin makes no sense. X58 is dead and should not be re-sold with a 133MHz bump. Top proc ever for X58 was X5690, 133MHz higher than X5680 (W3680). It didn't even beat the W3680 by more than 2%.
 
Umbongo and goMac,

G3 was an entirely different arena and completely different company from Intel, can't really relate update frequency on the G3 to Intel's.

Like I've been trying to suggest, the "Intel Instruction set" -- there is no major R&D work around producing an EFI to work with Xeon CPUs nor the motherboard chipsets -- maybe you folks were not aware that the initial driver set is actually provided BY Intel, Apple primarily just do the testing and feed results back to Intel engineers.

Yes I do know a key individual that works at Intel (in the senior engineering chain) and I can assure you there is nothing related to Apple and the new Xeon being tossed around his department ... he can't tell me what IS going on, but he certainly can tell me what is NOT going on ... and it ain't Apple.

It's just a myth to suggest Apple has some kind of huge R&D effort needed on minor and even major CPU updates ... if the addressable Instruction sets change then there might be some additional work IF those features are to be used, but for minor CPU updates that's never the case. For major CPU updates it's rarely a big deal in these cases as compatibility is ensured with the Intel platform ... that's the beauty of going with Intel.

A 460Mhz bump is VERY significant for any professional ... even more so when working multi-core capable applications. A processor upgrade does NOT destroy a profit margin, why should it?? Like anything Apple, they just increase the price and the Pro's pay for it ... time money. This specific may have needed an EFI update just to set the CPU table clock and multipliers but that's it (not exactly a huge R&D investment).

One thing Apple do well is ensure their ROI ... MacPro line has always been a huge ROI and their investment to update just isn't that much.

But again, if you don't believe me, just look at the iMac line and how quickly (relatively speaking, still pretty slow compared to the Industry as a whole) it gets CPU updates including new chipsets -- Apple know how to get updates out with minimal investment, and they KNOW how to make a profit.

As a former Shake 4 engineer once said (not me), "if you rely on Apple alone, you will only be disappointed". I believe it was this very site that rumored Shake's "new version" was going to be called "Phenomenon" ... optimistic hope of an product that was EOL. Apple will not announce EOL for the MacPro, they'll just silently remove it from their online store.
 
Umbongo and goMac,

G3 was an entirely different arena and completely different company from Intel, can't really relate update frequency on the G3 to Intel's.

Like I've been trying to suggest, the "Intel Instruction set" -- there is no major R&D work around producing an EFI to work with Xeon CPUs nor the motherboard chipsets -- maybe you folks were not aware that the initial driver set is actually provided BY Intel, Apple primarily just do the testing and feed results back to Intel engineers.

Yes I do know a key individual that works at Intel (in the senior engineering chain) and I can assure you there is nothing related to Apple and the new Xeon being tossed around his department ... he can't tell me what IS going on, but he certainly can tell me what is NOT going on ... and it ain't Apple.

It's just a myth to suggest there is some kind of huge R&D effort needed on minor and even major CPU updates ... if the addressable Instruction sets change then there might be some additional work IF those features are to be used, but for minor CPU updates that's never the case. For major CPU updates it's rarely a big deal in these cases as compatibility is ensured with the Intel platform ... that's the beauty of going with Intel.

A 460Mhz bump is VERY significant for any professional ... even more so when working multi-core capable applications. A processor upgrade does NOT destroy a profit margin, why should it?? Like anything Apple, they just increase the price and the Pro's pay for it ... time money. This specific may have needed an EFI update just to set the CPU table clock and multipliers but that's it (not exactly a huge R&D investment).

One thing Apple do well is ensure their ROI ... MacPro line has always been a huge ROI and their investment to update just isn't that much.

But again, if you don't believe me, just look at the iMac line and how quickly (relatively speaking, still pretty slow compared to the Industry as a whole) it gets CPU updates including new chipsets -- Apple know how to get updates out with minimal investment, and they KNOW how to make a profit.

As a former Shake 4 engineer once said (not me), "if you rely on Apple alone, you will only be disappointed". I believe it was this very site that rumored Shake's "new version" was going to be called "Phenomenon" ... optimistic hope of an product that was EOL. Apple will not announce EOL for the MacPro, they'll just silently remove it from their online store.

Can't say that you are right until E5 drops. Everything is just conjecture right now. Including your "insider" knowledge. I have friends that work at Intel too. The right hand does not talk to the left.
 
Umbongo and goMac,

G3 was an entirely different arena and completely different company from Intel, can't really relate update frequency on the G3 to Intel's.

Why not? At the time people were complaining, ATI was shipping a retail Radeon card. All the hardware was in place, Apple just didn't update.

It's just a myth to suggest Apple has some kind of huge R&D effort needed on minor and even major CPU updates

I totally agree, but that doesn't change Apple has never once done minor upgrades. They just don't.

Trust me, I have stories of minor updates being handed to Apple on a silver platter, and they still don't do them.
 
Can't say that you are right until E5 drops. Everything is just conjecture right now. Including your "insider" knowledge. I have friends that work at Intel too. The right hand does not talk to the left.

Can't really say it's "insider" knowledge since it's not Apple and my connection was only confirming what is "not" happening - no special Apple/Intel Xeon deals -- but when you take into consideration E5 Engineering Sample have been distributed one would think Apple would be in that list IF they had plans for it -- wouldn't one?

----------

Why not? At the time people were complaining, ATI was shipping a retail Radeon card. All the hardware was in place, Apple just didn't update.

I totally agree, but that doesn't change Apple has never once done minor upgrades. They just don't.

Trust me, I have stories of minor updates being handed to Apple on a silver platter, and they still don't do them.

I have no doubt Apple just don't update even when easy to do so ... that's painfully obvious, even in their iMac line.

But the company Apple back when the G3 was around was a VERY different company than the Apple of today ... how many of you folks (back in the G3 days) would have predicted Apple would be financially stronger than both Google AND Microsoft combined by 2012?
 
But the company Apple back when the G3 was around was a VERY different company than the Apple of today ... how many of you folks (back in the G3 days) would have predicted Apple would be financially stronger than both Google AND Microsoft combined by 2012?

I did. That's why career moved in that direction. Foresight working, finally:D
Apples silence is always unwelcome for folks like me when budgets are due and no info can be found. Their white papers pretty much sum up the communication. The fact that we have this site just to wade through the lack of communication is very telling.
 
But the company Apple back when the G3 was around was a VERY different company than the Apple of today ... how many of you folks (back in the G3 days) would have predicted Apple would be financially stronger than both Google AND Microsoft combined by 2012?

I don't disagree, but again, I don't think that has anything to do with Apple's lack of minor speed bumps. It's just the way Apple has always been. It's co-encidence, not a correlation.
 
Umbongo and goMac,

G3 was an entirely different arena and completely different company from Intel, can't really relate update frequency on the G3 to Intel's.

Like I've been trying to suggest, the "Intel Instruction set" -- there is no major R&D work around producing an EFI to work with Xeon CPUs nor the motherboard chipsets -- maybe you folks were not aware that the initial driver set is actually provided BY Intel, Apple primarily just do the testing and feed results back to Intel engineers.

Yes I do know a key individual that works at Intel (in the senior engineering chain) and I can assure you there is nothing related to Apple and the new Xeon being tossed around his department ... he can't tell me what IS going on, but he certainly can tell me what is NOT going on ... and it ain't Apple.

It's just a myth to suggest Apple has some kind of huge R&D effort needed on minor and even major CPU updates ... if the addressable Instruction sets change then there might be some additional work IF those features are to be used, but for minor CPU updates that's never the case. For major CPU updates it's rarely a big deal in these cases as compatibility is ensured with the Intel platform ... that's the beauty of going with Intel.

A 460Mhz bump is VERY significant for any professional ... even more so when working multi-core capable applications. A processor upgrade does NOT destroy a profit margin, why should it?? Like anything Apple, they just increase the price and the Pro's pay for it ... time money. This specific may have needed an EFI update just to set the CPU table clock and multipliers but that's it (not exactly a huge R&D investment).

One thing Apple do well is ensure their ROI ... MacPro line has always been a huge ROI and their investment to update just isn't that much.

But again, if you don't believe me, just look at the iMac line and how quickly (relatively speaking, still pretty slow compared to the Industry as a whole) it gets CPU updates including new chipsets -- Apple know how to get updates out with minimal investment, and they KNOW how to make a profit.

As a former Shake 4 engineer once said (not me), "if you rely on Apple alone, you will only be disappointed". I believe it was this very site that rumored Shake's "new version" was going to be called "Phenomenon" ... optimistic hope of an product that was EOL. Apple will not announce EOL for the MacPro, they'll just silently remove it from their online store.

The iMac has gotten updates more quickly because intel has release those chips more quickly, afaik they didn't bump nehalem i5/i7 (mid 2010), they introduced sandy bridge instead, and didn't bump those cpus speed either yet, seemingly they'll introduce ivy bridge.

It is a bit weird that apple decided not to bump the Xeons in the Mac Pro a little bit recently.
 
robains,

I should have been clearer about what I was talking about. I agree there is no development cost for new processors - that is a financial issue because of how Apple sell their systems compared to companies like Dell and Fujitsu. HP do have some boxed systems, but they don't have their own store inventories. Apple issuing minor updates makes old stock redundant quicker.

The actual upgrades possible aren't that amazing:
2.8Ghz 4-core to 3.06 then 3.2.
3.2GHz 4-core to 3.2 6-core and then 3.33 6-core is the best of them all.
3.33GHz 6-core to 3.46GHz
2.93GHz 12-core to 3.06GHz - I know there are faster processors, but Apple haven't used processors with those thermal characteristics since 08.

I was more thinking along the lines of graphics card update and inclusion of thunderbolt which would have had to come too. Those would require development and together with the 4 possible processor changes would have made some more interesting Mac Pros, but I doubt they would have increased sales with any significance over what was expected in this now niche line. It also isn't the first time processors have updated and Apple haven't made changes but waited for a major change. They have only refreshed once per architecture since the switch to Intel for Mac Pros. Nothing completely out of the ordinary so far.

As Intel have continuously pushed back SB-EP we can't say what Apple is or isn't doing with certainty. The only Mac Pro rumour I can even think of that came true in the past 5 years was the one that said they bought all 1600MHz Penryn Xeons, and Apple were the only ones to ship and list for a while. We've also seen information on graphics drivers that would only be for Mac Pro cards.
 
Maybe I didn't understand your original statement then:
Apparently not. ;) :p

To me, it sounded like you suggested that TB is one-directional while PCIe is bi-directional, which is not true. Your above storage example should apply to PCIe as well, in that case. I know bi-directional is all that important in real world and it most certainly doesn't double the bandwidth.
I wasn't trying to imply that TB is uni-directional, or is switched, as low-cost bi-directional interfaces tend to do in order to meet production cost requirements (one or the other at any given time, never simultaneous).

I only tried to show that TB is capable of more than 800-850MBps which is what you claimed. We should be talking about the limits of TB, not about the limits of Deathstars ;) It's not a surprise that you aren't getting more than ~800MBps from RAID'ed HDs, especially Hitachis. The actual interface is capable of more, though (about 1GBps).
Intel only published 800MB/s from what I recall, though their own testing as well as the Pegasus R6 (mechanicals) showed it was good to ~850MB/s.

As per the SSD source you posted, the cache had an influence there that won't be represented in TB's actual throughput, as TB does add latency, and not just the hardware (they advertise 7 - 8ns IIRC, but that doesn't include protocol conversion).

It's even possible that burst rates were influencing the results as well, but cache is definitely there due to the RAID controller used in the R4 & R6, and would definitely have a noticeable effect on the test results.
 
Intel only published 800MB/s from what I recall, though their own testing as well as the Pegasus R6 (mechanicals) showed it was good to ~850MB/s.

As per the SSD source you posted, the cache had an influence there that won't be represented in TB's actual throughput, as TB does add latency, and not just the hardware (they advertise 7 - 8ns IIRC, but that doesn't include protocol conversion).

It's even possible that burst rates were influencing the results as well, but cache is definitely there due to the RAID controller used in the R4 & R6, and would definitely have a noticeable effect on the test results.

So you're saying the 200MB/s higher result with SSDs on the R6 is all due to cache??
 
I haven't seen that figure, maybe you are mixing it with early demos for example. Care to show where you got that 800MB/s from?
Of course it's from demo's :D, as Intel won't publish a full specification on TB (given technical details on the hardware itself, but nothing on protocol conversions to date). :( :mad:

But if you want a source, take a look here (specifically, take a look under the Third Party Support heading).
Thunderbolt supports two channels of 10Gbps (equivalent to about 1280MBps) transfers in both directions, simultaneously. Intel demonstrated actual throughputs of up to 6.25Gbps (800MBps) using prototype consumer products.
BTW, the math checks out, so the author wasn't smoking anything. ;)

(10Gb/s / 8) * 1024 = 1280MB/s (max sustainable bandwidth), which is in excess of what the PCIe lanes can actually handle. Sounds great.

But there's still the latency to be taken into account (8ns, which I verified to day), and more importantly, there's absolute silence on the protocol aspects of it, and if you recall, TB is a dual-protocol interconnect (conversions on both ends).

Let me give you an example using SATA's 8b/10b encoding alone with the above calculations...
8b/10b * 1280MB/s = 1024MB/s. Still decent vs. 800 - 850 or so (though 800 - 850 isn't a slouch by any means).

Now take into account the latency (and it's per packet BTW), you'll get less in terms of real world throughputs.

Where it gets murky however, is with the TB to PCIe protocol conversion, as Intel hasn't produced any public data on this.

So all we can go on is real world testing that's currently available, which I suspect you'll agree with. ;)

My previous point was with the example you used that got it over 1GB/s, as it took cache into account.

A more accurate test IMO would be multiple SSD's over TB, but not attached to any sort of RAID hardware (takes cache out of the equation, save the cache on the SSD's themselves), and operated independently in a Daisy Chain on the same TB port, but simultaneously (i.e. read/write at least one very large file per disk simultaneously).

Or better yet, any other test that can achieve more than 1GB/s over TB that doesn't use cache whatsoever in order to try and determine what TB's actual limits are for real world performance (what's more important to users anyway).

Unfortunately, I don't have access to the hardware, but perhaps you do, given your connections with Anandtech. :) Hint hint. ;) :D

So you're saying the 200MB/s higher result with SSDs on the R6 is all due to cache??
Yes. It could easily be that high, and there are systems that can exceed that substantially.

For example, I have a volume that's built of 8x disks in a RAID 5, and can generate 1.39GB/s during a write due to cache (2GB of it BTW). But when I turn it off, that performance figure is cut to nearly half (~780MB/s). So we're looking at a 620MB/s or so boost just do to cache, which is substantial.

Granted, my RAID card is more robust than the controller that's in the Pegasus, but cache can have that great of an influence on performance data.
 
Yes. It could easily be that high, and there are systems that can exceed that substantially.

For example, I have a volume that's built of 8x disks in a RAID 5, and can generate 1.39GB/s during a write due to cache (2GB of it BTW). But when I turn it off, that performance figure is cut to nearly half (~780MB/s). So we're looking at a 620MB/s or so boost just do to cache, which is substantial.

Granted, my RAID card is more robust than the controller that's in the Pegasus, but cache can have that great of an influence on performance data.

You realize that the cache would be on the Pegasus R6 side right? those 1000MB/s are actually going to the Pegasus R6 through Thunderbolt.
 
You realize that the cache would be on the Pegasus R6 side right? those 1000MB/s are actually going to the Pegasus R6 through Thunderbolt.
Yes I do, but you have to realize, that it doesn't actually matter. :eek:

Once it's in the cache, the system sees the operation as completed, even if the disks themselves haven't completed the writes. This is due to the fact the write operation is actually executed to the cache (under normal operating conditions = cache is present and active). When it's there however (cache is present, which is not the case with software based RAID implementations), it's usually possible to Disable the cache to properly performance test the volume for writes (sometimes this is possible through the performance test suite, otherwise you have to access the card's settings to disable it).

Which is why it gives false throughput data during write testing (controller's cache).

So regardless of where it's located, it still has a notable influence.

Disk cache itself also helps, and in particular, push up read throughputs, but not to the extent of a controller's cache when present, as it's much smaller capacity wise. Unfortunately, this typically can't be Disabled.
 
Yes I do, but you have to realize, that it doesn't actually matter. :eek:

Once it's in the cache, the system sees the operation as completed, even if the disks themselves haven't completed the writes. This is due to the fact the write operation is actually executed to the cache (under normal operating conditions = cache is present and active). When it's there however (cache is present, which is not the case with software based RAID implementations), it's usually possible to Disable the cache to properly performance test the volume for writes (sometimes this is possible through the performance test suite, otherwise you have to access the card's settings to disable it).

Which is why it gives false throughput data during write testing (controller's cache).

So regardless of where it's located, it still has a notable influence.

Disk cache itself also helps, and in particular, push up read throughputs, but not to the extent of a controller's cache when present, as it's much smaller capacity wise. Unfortunately, this typically can't be Disabled.

Wasn't this about how Thunderbolt couldn't reach 1000MB/s, but it actually does???
 
Wasn't this about how Thunderbolt couldn't reach 1000MB/s, but it actually does???
We don't know for certain one way or the other, but I suspect that it doesn't due to the protocol conversions on both ends, combined with latency added by the device itself, such as the 8b/10b encoding of SATA controllers on the disks themselves.

If this were truly the case, Intel would publish that with gusto. They haven't.

So though we don't know every single detail as Intel won't release it, lets go through a couple of quick things.
  1. TB connects to 4x PCIe Gen 2.0 lanes, which is good up to 2GB/s.
  2. TB is rated for 10Gb/s max per direction (1.25GB/s).
  3. Take into account it adds 8ns latency per packet, that will reduce it. BTW, this isn't the TB to PCIe conversion rate, but point to point connection latency (TB chip over the cable to the endpoint device, and it's per link; so this will be multiplied with daisy-chained devices).
  4. But where it really becomes important, is the protocol conversions on each end. And what Intel hasn't published, is the TB to PCIe conversion data rate.
Case in point, is SATA. On the SATA end, there's the 8b/10b encoding scheme to deal with, which alone brings that 1.25GB/s figure down to 1GB/s max. Then there's the TB to PCIe protocol conversion to deal with, and Intel's not talking on that one. Top it off with the 8ns latency aspect of TB, and other limitations in the end-point device (i.e. mechanical HDD's can't saturate their interfaces for example, and only a few SSD's can), all of my education and experience in engineering tell me that it's not going to hit 1GB/s in either direction for sustained throughput figures.
 
It looks like Intel went as far as to make an entirely new die for the 4-core Core i7 3820 instead of harvesting from the 8-core SB-E ones.

New die or the 8 core die cut down? I think it is the later (i.e., new is a bit of an overstatement). Notice how cache size is modular with core count. The cores and cache "modules" are on a ring bus. If you just cut out some cores and cache modules you can get a smaller (cheaper) die. It is new in the sense that it is different, but is taking 4 pearls off a 28 pearl necklace really a "new" necklace?
 
New die or the 8 core die cut down? I think it is the later (i.e., new is a bit of an overstatement). Notice how cache size is modular with core count. The cores and cache "modules" are on a ring bus. If you just cut out some cores and cache modules you can get a smaller (cheaper) die. It is new in the sense that it is different, but is taking 4 pearls off a 28 pearl necklace really a "new" necklace?

New means that it's not an 8-core die with four cores disabled like the hex-core parts are. Of course it's still the same 32nm Sandy Bridge E.
 
New means that it's not an 8-core die with four cores disabled like the hex-core parts are. Of course it's still the same 32nm Sandy Bridge E.
Either way, it's the same architecture. ;)

But using a smaller die rather than just disabling cores will give higher yields per wafer if there's enough demand to justify the separate wafer process (same equipment and unprocessed wafers, just different gels that allow more parts per wafer as each isn't consuming as much surface area as the 8 core variants). Obviously they think this is the case (will include the LGA2011 Xeon 4 core variants, so there will still be some differences, such as ECC support; just cut a few copper traces for example, aka jumpers, if ECC is to be Disabled).

Ultimately it lowers the production cost per 4 core LGA2011, and increases Intel's profits. Win-win from their POV, though if I recall the pricing structures correctly, there doesn't seem to be any savings passed on to consumers (not unexpected IMO, given the shift to 32nm processing and the MBA mindset I've experienced).
 
That 2620 with only a 2.0 GHz clock rate scares me a little. Even though I'm closer to the core count than the core speed camp when it comes to work flow, a 2.0 clock speed has me worried. ....

... along with some other posts musing as to how the 2.0-2.2GHz of the new E5 2600's might be too slow for single threaded work....


It is bit early to "write off" these 2620/2650 updates because the base clock is lower without knowing where the Turbo range is.


New Anandtech benchmarks on a server. [ Might not be such good results on older , Pentium 3 or 4, optimized code but on modern compiled software looking to leverage the float abilities..... ]


44348.png

http://www.anandtech.com/show/5553/the-xeon-e52600-dual-sandybridge-for-servers/10

If the vast majority of the workload is single thread then the E5 1620 is probably the much better option (in a bang for the buck context). But it seems straightforward at this point that if only have workload on a single core the turbo capabilities of the E5 is substantially better than what Turbo was in the X5600 series.

Apple doesn't "have to" go to the 130W bleeding edge to turn in performance greater than the former Mac Pro top of the line : X5670 .
The E5 2665 or 2670 ( 2.4, 2.6GHz base at 115W) would probably put a decent gap between the old top range and the new just on single thread without having to resort to matching base clock rates exactly.
 
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