Memory density without ECC is a waste of time. Hence, not going to get anywhere near > 1TB RAM at all.
What makes you think Apple wouldn't incorporate ECC if they went to ≈1 TB? That's what NVIDIA did with the (up to) 960 GB LPDDR5x RAM in its Grace Hopper Superchip.
Indeed, Apple recently published a patent about the use of ECC in LPDDR RAM. While the patent makes a passing mention of on-die ECC, most of it focuses on their claims of improvements to link ECC:
[
https://patentscope.wipo.int/search/en/detail.jsf?docId=US403904970&_cid=P12-LLBQX0-80508-2 ]
Expanding on this:
AIUI, there are two broad types of ECC: (1) traditional "transmission" ECC (which corrects transmission errors between the RAM and the processor; when RAM is labelled "ECC", they're referring to this); and (2) on-die ECC, a new type of ECC that was introduced with DDR5 to address, as the name indicates, on-die memory errors that DDR5's higher memory density makes more prevalent.
Transmission ECC comes in two flavors: side-band (typically used in DDR RAM) and inline (used in LPDDR RAM). The variant of inline ECC that JEDEC introduced for LPDDR5 is called link ECC (I don't know if inline ECC was available to earlier generations of LPDDR).
But that leaves me with these specific questions:
1) Are there differences in the robustness of error correction between the JEDEC DDR5 standard's "transmission" ECC, and the JEDEC LPDDR5 standard's link ECC?
2) How exactly does Apple's patent claim to improve upon link ECC? It would be nice if it came with a clear abstract that said: "This is how the patent improves upon relevant existing technologies and prior art: ..." It does say that existing ECC used in servers consumes too much power for many applications, but doesn't summarize how this is an improvement over the
relevant existing tech, which is link ECC (and which, as it's designed for LPDDR RAM, likely consumes much less power).
And these more general ones:
1) On-die ECC helps with RAM manufacturing. But is it also used to address memory errors (e.g., on-die bit flips) that occur during use?
2) Does the JEDEC standard for LPDDR5 specify on-die ECC?
3) Is there currently any LPDDR5 link ECC RAM on the market? I can't find any. Or is it the case that *all* LPDDR5 RAM comes with link ECC, but because its error correction is not as robust as that of standard DDR ECC, they decided not to label it as "ECC"? Note I'm referring to LPDDR5, not the LPDDR5x ECC RAM that NVIDIA uses.
For more info.:
Technical Bulletin: Error Correction Code (ECC) in DDR Memories
www.synopsys.com
Technical Bulletin: Key Features Designers Should Know About LPDDR5
www.synopsys.com
Unidirectional is TBv5 is better than DPv2.1 how?????
Sheesh, who pissed in your cereal? Really, you should try to be environmentally responsible and not waste question marks. Five is excessive, some might say profligate.
This seems like a complete non-sequitur to my post. Nowhere, in suggesting TB 5, did I rule out DP 2.1 Indeed, when TB5 is released, it should accomodate DP 2.1.
Note also that, while the TB5 standard hasn't been released, it appears it will be able to dynamically rebalance from 80 Gbps each way to 120 Gbps out/40 Gbps in. If Apple's next XDR is, as some rumors say, a 10-bit 7k 120 Hz display, you could run it uncompressed (no DSC) using TB5, as that requires 111 Gbps. DP 2.1, by contrast, is limited to 80 Gbps each way.