@deconstruct60
So Mn Max laptop variant & Mn Max desktop variant...?
At some point along the way Apple is going to hit forces that are going to push the Max-sized die up into chiplets.
Same reason why AMD is going that way now with their top end GPUs.
AMD RDNA 3 GPU Architecture Deep Dive: The Ryzen Moment for GPUs | Tom's Hardware (tomshardware.com)
N3 is more expensive than N5. And N2 is going to be even more expensive. At some point huge monolithic dies with all of the L3/"System level cache" that Apple is lugging around isn't going to make sense moving to N2 (and smaller). It has already hit diminishing returns zone.
Very similar diminishing returns zone for outward/external facing functionality like PCI-e lanes. (closer to Analog I/O on that graph than logic. ). Implementing 8 or 16 Thunderbolt controllers in N3 or N2 probably into the zone where there is less and less "bang for the buck" there.
Amazon Graviton 3 somewhat similar issue handling. Memory and PCI-e chiplets are attached to the central die that just has the compute core and internal mesh.
Pretty good chance Apple is going to play this like Nvidia and stick with monolithic as long as they can. Mx Pro size die and smaller (at the prices Apple is charging) will be more doable for longer. Mx Max size die ( 400mm^2 ) is going to hit the 'wall' substantially sooner. The more die external I/O the larger the pressure.
For example, a 'desktop' Max class SoC where the Thunderbolt controllers were attached by a N4 chiplet could be 6 ports on both the "Max" and "Ultra" set ups and the Studio would be more uniform in port provisioning. Primary reason now decoupled is that it is being driven by MPB 14"/16" port allocations. [ and not just the TB controllers. Really only need one SSD controller , on Secure Enclave Processor , etc. Replicating that 4 times on N3 expensive (or more in future iteration) silicon is just plain dubious if not going to use it. The compute cores (CPU/GPU/NPU) need to be replicated.. the single use I/O definitively does not. ]
Also opens door to put a x16 PCI-e v4 chiplet on instead if need more than just one external chiplet in multiple die set ups. Again can leave that back on N4 and save money.
The laptop dies will use PCI-e v4 , v5 progress to hold the number of die external I/O constant ( or fewer). Could shrink from four x1 PCI-e v4 lanes to just one x1 PCI-e v5 (and Apple slaps a external PCI-e switch to dole out four v3 lanes or something more flexible. ). For the desktops ( and especially Mac Pro ) they aren't going to be able to 'shrink' their way out of the problem as easily.
Early on there were rumors about four code names for the post 'plain' M1 dies. Jade , Jade-chop , Jade2C , and Jade4C. I think what Apple delivered was Jade-chop (M1 Pro) and Jade-2C ( used as a Jade for M1 Max and dual for Ultra). They went cheaper and just did two dies into high volume ( and relatively low volume for a 3D mini-interposer for the Ultra) . Jade4C didn't ship in volume because ran into cost and complexity problems (and delayed too long as a cherry on top). Those cost problems only get worse with TSMC N3 and following if try to brute force laptop monolithic dies into "chiplet" roles.
[ And very similar issues if Apple has been trying to brute force their cellular modem onto the same process node as one monolithic iPhone die. Makes less and less sense going forward given increasing costs and divergence issues. ]
I hope so, would be nice to see Apple focus on a desktop/workstation variant of Apple silicon...
That's is leading away from what I'm saying. It is closer to desktop than "reuse Server CPU processor" in an expensive workstation. They going to need 'iMac' like volume to pay for the gap between the design. This is not a foray into making "Threadripper" and "Xeon SP" killer SoC. Apple would scale the Mac desktop up to fill the "workstation" role. It isn't a primary focus on high end workstation only that peels backwards to fill a desktop role.
M3 Ultra/Extreme should really shine on the N3X process...?
Zero idea about why you keep chattering about N3X. Apple is pretty unlikley to use it at all. N3P? far better likelihood. N3X? No. I highly doubt Apple is going to separate the process nodes used for laptop and desktop from each other at all for the CPU/GPU/NPU cores that do the compute. It is the higher I/O controller overhead costs for the desktops that shift to save costs ( use previously mastered fab processes to do those to be more cost effective).
The notion that Apple is going to radically throw all the laptop stuff out the window and start over from scratch for desktops makes no economic sense at all. Just fanboy hype. The issue is scaling the
reuse ... not throwing it all away and starting over.
N3X would never work well on a 'plain' Mn or An implementation. So Apple isn't going to touch it with zero reuse viability.
It isn't 'if' some eventual Mx desktop SoC goes over to more disaggregated chiplets, it is more just a matter of 'when'. AMD is using the same exact fab company as Apple and they have seen the light. Apple isn't immune to the same basic fabrication hurdles.