Apple also has the option to adjust it to be less aggressive in transistor count, core counts, engine counts and power input for aggressive raw performance improvement to run at a slightly smaller die & slightly lower power consumption.
Which node could Apple use?
www.semianalysis.com
I would think it would be extremely difficult to compare between them, as they have different core speed, core numbers and consuming different energy achieving different TFLOPS values. Furthermore, most test likely favour nVidia's GPUs seeing that they have software being optimised for their GPUs for much longer.
I'll hold off any speculations to 2024 when all the online forums settle on what actually occured or else we'd have people claiming SoC's iGPU can never have dGPU-level raw performance because it has never been done before not for technical reason but because that's now how the parts business is done.Which node could Apple use?
View attachment 2155322
TSMC’s 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed
Shrinking finally costs more, Moore’s Law is now dead in economic termsA couple of weeks ago, we were able to attend IEDM, where TSMC presented many details about their N3B and N3E, 3nm class…
Although I have not found numbers for a comparison between GPUs, Luke Miani has done a general comparison between a laptop with RTX 4090 and the best MacBook Pro.
Compare a laptop that comes standard with a 96W charger that has an option for 140W charger for fast charging... with up to 22 hrs of battery life
I think Apple will keep the same number of cores as the M2 series. They already bumped up the core count for Pro/Max which will lead to a bump for the Ultra as well.
Each generation of chip will have more core counts unless it is for market condition reasons.
Do you have a source for this?
I'm not wondering. See my thoughts here: https://forums.macrumors.com/thread...omms-8cx-gen-4-based-on-nuvia-design.2377972/
One chip from Qualcomm's 2024 NUVIA roadmap that is inferred as being positioned to take on M1/M2 of 2024. I expect M3 to be released by then unless Apple aligns their supply chain for annual refresh of Mac chips
Again, see my thoughts here.
Do you have a source for this?
I am 95% sure that's wrong. AFAIK, there is no meaningful difference in latency to any of the memory controllers from any of the cores, so it is in no way NUMA. Now, on the other hand, as I pointed out, the situation's almost certainly different for the Ultra. I believe there is a latency penalty for accessing RAM across the "ultrafusion" link. (If anyone knows for sure one way or the other please say so, with a cite!)
Indeed it does make it different! That propagation delay (which isn't just a propagation delay, as more logic is involved, not just wires) makes half the system RAM have a latency greater than the other half, for any given core. That is the definition of NUMA.
That's debatable. Or at least, it needs more data. But there's no question that making it NUMA-aware would wrest more performance out of the system, and Apple is relentless in their pursuit of that kind of efficiency. Of course, the OS crew will know this is coming (if it is) and have some time to work on it before it ships.
No, that can't happen. I agree that there will likely be more cores, but N3B (or any N3) is not going to buy you double the cores. It's not that much smaller. And in particular, N3B saves almost no space over N5x for static RAM, which is a major part of each core cluster (as well as the SLC).
Which node could Apple use?
View attachment 2155322
TSMC’s 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed
Shrinking finally costs more, Moore’s Law is now dead in economic termsA couple of weeks ago, we were able to attend IEDM, where TSMC presented many details about their N3B and N3E, 3nm class…
If my expectation is correct, the first M3 will be a huge multichip package for the Pro. But eventually we'll see a regular M3, on N3E, and it will be interesting to see what that looks like - all the factors I mention above apply here as well. The M3 will likely have a significant IPC boost, and probably a modest clock boost as well. They could easily leave it as 4/4, but I think 6/4 or 8/4 is more likely (6/4 only if they change the clusters to 3x from 4x). But the same outside chance of lots of E cores is possible here too - say, 4/8 or even 4/12.
Except you know, those aren't game consoles but phones that the majority of users will never crack open a game let alone one that needs hardware more advanced than a PS2.
Ummmm. the M1/M2 are essentially A14X/A15X with specializations to make them more usable in a Mac... before the iPad Pro we got several iPads with the X series of chips with more CPU/GPU cores, and when we got the A12X/Z iPad Pro we got double the CPU and GPU cores of the iPhone.... The iPad has a long history of high performance chips before the M series showed up.
There are multiple "interesting" things here. Average latency is important. But I was just focusing on whether memory access was visibly NU or not, because if it is, then that's something you either have to deal with, or choose to ignore, at some cost (which you're presumably accepting as a tradeoff).
Maybe. But as I said, since most of the time when reaching across the bridge you're still going to cache, a little extra latency might not really be negligible.
Irrelevant in the moment, but amusing. I saw that patent about dropping resolved bits too. My level of understanding (not as high as I'd like it to be!!) is such that I was surprised that this optimization actually matters enough to be worthwhile. I mean, it's a partial word against at least a half cache line. Amazing.
OK, that counts as NUMA-aware. But it's a somewhat different focus of optimization. I still think, unless there's a problem with my argument about going to cache across the bridge, that you're going to see a meaningful latency issue with nonlocal memory. Not necessarily a huge issue, but a meaningful one (compared to, say, other things they spend effort optimizing out).
I don't agree with him that the MSI Raider is the PC counterpart to the MBP, the MBP weights over 2 pounds less, it is an inch less wide, 2 inches less deep and almost an inch thinner. These aren't competitors...
Wouldn't be surprised if instead of adding cores, Apple ends up having the same amount cores on a smaller die. They have a history of doing this in order to cut costs when moving to a next-gen node (next-gen node == more expensive, so get more chips out of a wafer to offset it). The improvements from cramming more into a die usually come the 2nd year after moving to a new node when the price per wafer went down.
| A9 | 16nm | 104.5mm2 | |
| A10 | 16nm | 125mm2 | Stayed on same node --> Increase die size |
| A11 | 10nm | 87.66mm2 | New node --> Shrink die size |
| A12 | 7nm | 83.27mm2 | New node --> Shrink die size |
| A13 | 7nm | 98.48mm2 | Stayed on same node --> Increase die size |
| A14 | 5nm | 88mm2 | New node --> Shrink die size |
| A15 | 5nm | 107.68mm2 | Stayed on same node --> Increase die size |
| A16 | 5nm (4 but actually 5) | >107.68mm2 | Stayed on same node --> Increase die size |
