I don't want it because it can't be done without compromises. I'd much rather have a desktop without the compromise for 99% of what I do.
Got a tip for us?
Let us know
Become a MacRumors Supporter for $50/year with no ads, ability to filter front page stories, and private forums.
Rumored pro chip
- Thread starter cmaier
- Start date
- Sort by reaction score
"Samsung introduced its latest memory solution today, called LPDDR5 UFS-based multichip package, or uMCP. It integrates LPDDR5 RAM and UFS 3.1 NAND flash on a single chip"
This was apple hinting in state of the union...so probably this is the next step for apple as well, gpu, cpu, ram and ssd
This was apple hinting in state of the union...so probably this is the next step for apple as well, gpu, cpu, ram and ssd
That makes no sense. Improving the efficiency cores is a great way to improve performance. Reducing the number of efficiency cores means the performance cores have to spend time on menial work.
Thinking is what cpu designers do, by the way, so I don’t think I’ll stop.
That would be super cool. I guess this is a tech preview and nowhere near mass shipments though.
Let me rephrase that a bit. I can't always get what I want and sometimes the the requirements of traveling needs a laptop. 99% of the time I'd be using it plugged in, but yes, it would be nice to have desktop power in a small and light laptop, but it sounds expensive if it could ever be done!
I could see the 16” coming down that much but would they limit them 14” to that? Even with the rumoured better cooling system of them 16” supposedly coming to it?
It will get the strongest chip in the iPad lineup and this appears to mean it will get whatever is the latest base M-Series SoC (so M1, M2, M3).
It's all about the number of cores so 8 Firestorm (M1x) performance cores are going to comfortably outperform 4 Avalanche (M2) performance cores.
On a iPhone or iPad ? Pretty big maybe. iPhones haven't used separate RAM modules so no "space" to save there. The RAM dies are typically layered on the SoC. If the Apple SoC ran much hotter maybe they would be looking for a new home, but that would be quite odd with Apple using the most bleeding edge volume fab production to do iPhone SoC. When Apple comes up with an highly coupled and/or integrated celluar modem that will drop some more. ( and Apple has managed to do 5G mmWave ( with "extra" radio handlers ) in a iPhone 12 mini ) .
iPads typically use iPhone SoC. So see above. The iPad Pro has had room for RAM and NAND separate. (and is pretty much lined up with entry Mac laptops now. ). The logic board is bigger than a phones ( and this Samsung product is primarily aimed at phones.)
On a Mac? Highly likely not. The large motivator to put the NAND in the RAM package is to hyper lack of logic board space. Mac's had T2 , Thunderbolt controllers, more than several RAM chips and at least a couple of NAND chips on their logic boards. IF the M-Series shrinks the T2 and Thunderbolt controllers alone onto the package that is a savings there. The other major design mismatch is that the M-series has to maximize the amount of RAM dies in the RAM modules. ( due to using relatively slower LPDDR4 (or later 5) they need a larger number of DRAM controllers and short path isolated DRAM trace paths. ). Apple has out of the mainstream DRAM modules already .
Are the Mac SoC integrating most stuff onto the SoC package? Yes. Will that suck in the NAND chips... probably not due to capacity. At the price point Apple is charging the entry base capacity of 256GB is somewhat lamely low. The max SSD capacity goes up to 2TB ( which these "mixed chips" aren't particularly adapt at provisioning. ) . What the Mac needs is NAND chips with more NAND dies in them; not less.
By using a new architecture instead?
And probably not just about "CPU cores" either. The display driving capabilities of the M2 is likely relatively limited also. Fewer Thunderbolt port support. M2 powered MBA or iPad Pro driving 2-3 displays with 1-2 TB ports is probably sufficient.
The large package will drive 3 (maybe 4 in some systems ) TB ports and more displays.
The "uncore" aspects of the SoC matters. Internal interconnects and I/O in the "M2" probably doesn't scale.
Also how does Apple justify a A12 in the new AppleTV instead of a A12X ... better profits and availability.
That is only true if the E cores can pull workload from the P core and also then turn the P core with enough resources to do something else ( or optionally turn off ). "Menial" work spilling over into the P cores is always potentially there if there is enough large amount of menial stuff around that needs handling.
Where the workload has certain kinds of locking that has P and E cores sharing memory that won't happen. So there is a factor here of "what workloads do most folks run who buy these systems" that plays a role also.
The other likely problem with the massive spike in GPU cores is that if there is sufficiently high L3 cache pressure offloading into the E cores would only help if their tasks were almost pure L2 footprint only. If the system L3 cache is overloaded , adding more cores isn't going to help much. Apple has no SMT to hide bigger latencies
If the memory subsystem isn't quite keeping up with the added scale then dropping E cores ( and swapping for incremental bigger L3 cache) would be a reasonable trade off.
The huge assumption here is that the memory system for a "Not so big package with a finiite set of memory I/O due to dense placement of only one package" can soak up a whatever core count you throw up on the board. That is probably not true.
Completely unified memory is a dual edge sword. If everybody shares the same L3 cache then everybody shares the same L3 cache. It is good in some cases ( easy sharing of data ) and bad in others ( when there is practically no data to share ; evitcing other worker's stuff. ).
Justify? With a mini-LED display coupled with the SD card and HDMI ports folks have been pounding the table with. For probably over 98% of the potential buyers they don't care which microarchitectural implementation it is. If it is way faster than the last MBP 16" and the M2 isn't going to touch it in terms of performance .... they probably don't care as much as features they can see and touch.
"Year old" is primarily only relevant if had released something previous. Apple has no significantly greater than 140mm2 solution they have previously done. The macrumors forums discussion and threads about the larger M-series SoC may be a year old , but that is highly insular to these forums. The vast majority of potential customers are not in some kind of "FOMO" angst about the which process node the chip is using.
The "core" doesn't matter as much as the uncore aspects of this new chip. That's where the primary differences are likely going to present themselves. Scaling up the count and filling in the substantive gaps in I/O coverage (and backsliding on Max RAM) are real aspects that will impact more mainstream workloads than geek porn benchmark scores.
That was a rethorical question more than anything. Apple isn’t the kind of company that justifies its design decisions. ?
Samsung begins mass production of LPDDR5 UFS-based Multichip Package memory - VideoCardz.com
Samsung Brings Flagship Features to Broader Smartphone Market With LPDDR5 Multichip Package Industry’s first LPDDR5 uMCP to be mass produced and deployed across mid- to high-end smartphones, starting this month Samsung uMCP combines LPDDR5 memory and UFS 3.1 NAND storage, providing industry’s...
The M1's on-board TB controller is said to only support TB3, so I would expect the "M1X" will also be TB3 unless Apple has a new TB controller ready that supports TB4. (Apple does use the Intel JHL8040R retimers which do support TB4.)
The M1 is PCIe 4.0 so I expect the "M1X" will also be PCIe 4.
Last edited:
Thunderbolt 4 maybe. One of the reasons why the M1 "fails" TB 4 compliance is the limited number of external displays it can support. If Apple makes some additions and only 'tags' on side as TB4 they may be able to pass certification. ( of course kneecapping iGPUs .... that could lead Intel to tip the scales to a 'fail' also. That is suppose to be on OS support. Issue though is that macOS x86 does support eGPU. The macOS M-series does not. Intel could look at that as essentially a fail. macOS is capable so it is expected. As opposed to macOS M-series gets a whole new clean slate for compliance. A "Thunderbolt 4" label should be given out to folks looking to backslide but still get a "get out of jail free" card. It is suppose to be a "does the complete set of things you expect it to do" label. Backsliding isn't meeting expectations. )
It won't make much of a performance difference labeled 3 or 4. It could indicate how much Apple (or Intel or both) are burning bridges behind them .
PCI-e v 5. LOL. I think should be hoping have PCI-e v3 in some healthy number of lanes. Let alone v5. From the leaks so far all Apple is interested in hooking up are SD-Card controller , ethernet ( up to 10GbE for Mini ) , and probably not much else. Little sign there is any discrete ( non Apple) GPU they are interested in enabling for the next year or so at all. Even the "half sized" Mac Pro may gut the GPU add-in-card ability. ( limit itself to add-in SSD and A/V capture cards. )
The iPhone and iPad's need PCI-e v5 even less.
If the only path out of the SoC to PCI-e for 3rd parties is Thunderbolt , then v3 is the limit.
Yes and no. It is a link inside the SoC. So technically yes. Is it useful for anything else but that specific SoC internal controller? Pragmatically not.
Thunderbolt doesn't "ride on " PCIe. It encapsulates the data and transports PCI-e protocol. It is a substantive transport in and of itself. ( it is not "external PCI-e". That is just an inaccurate connotation that gets regurgitated on these forums as if it as true; it isn't. ).
Will this (M1x) get us back to being able to use 3 or 4 external 5K displays do you think?
Highly unlikely. The Mini has a 10GbE ethernet socket option. That Ethernet is driven by a Ethernet controllers. Pretty unlikely that is coupled to the SoC by USB.
iMac M1 teardown. Step 8
iMac M1 24" Teardown
Is the new M1 iMac just a silly-sized M1 iPad, a detached-keyboard M1 MacBook, an M1 Mac Mini stretched out like pizza dough? We’ll only know by...
www.ifixit.com
Yellow square there is a Broadcom BCM57762 ethernet controller. It needs a x1 - x2 PCI-e lane bundle. ( 10GbE option in Mini M1 would be the x2 variant. No 10GbE in iMac. ).
Apple is also provisioning some of the USB sockets with a "ASMedia ASM3142 PCIe-to-USB 3.1 Gen 2 controller".
ASM3142|ASMedia Technology Inc.
ASMedia Technology was founded in 2004 and went public in 2012 (stock code: 5269.TW). Headquarter is located in Taiwan. ASMedia specializes in high-speed interface technologies with strong expertise in high-speed SERDES in house development. Company strives for continual innovation and the...
the baseline for the chip is the "1 to 2 port wonder" iPad Pro , but at some point they go past just two ports needed.
[ Thunderbolt needs USB 2.0 port provisioning also separate from the TB controller. ]
What the M1 doesn't have is anything like a x4 , or x8 , x16 PCI-e v4 lane allocation. But a couple of x1's and/or x2's are likely there. There are some NAND chip paths but the SSD controller is inside the M1 and there are no SSD NAND modules in the mix here at all either.
P.S. There is slim chance the Murata 339S00763 Wi-Fi/Bluetooth module is hooked up via PCI-e. However, that is probably custom apple for a only apple module. [ it is another mid-range I/O lane cluster coming out of the SoC though. ]
Last edited:
So if I’m understanding this correctly the M1 has PCI lanes, but at x1 or x2?Highly unlikely. The Mini has a 10GbE ethernet socket option. That Ethernet is driven by a Ethernet controllers. Pretty unlikely that is coupled to the SoC by USB.
iMac M1 teardown. Step 8
iMac M1 24" Teardown
Is the new M1 iMac just a silly-sized M1 iPad, a detached-keyboard M1 MacBook, an M1 Mac Mini stretched out like pizza dough? We’ll only know by...
Yellow square there is a Broadcom BCM57762 ethernet controller. It needs a x1 - x2 PCI-e lane bundle. ( 10GbE option in Mini M1 would be the x2 variant. No 10GbE in iMac. ).
Apple is also provisioning some of the USB sockets with a "ASMedia ASM3142 PCIe-to-USB 3.1 Gen 2 controller".
That also needs a x2 lane bundle.ASM3142|ASMedia Technology Inc.
ASMedia Technology was founded in 2004 and went public in 2012 (stock code: 5269.TW). Headquarter is located in Taiwan. ASMedia specializes in high-speed interface technologies with strong expertise in high-speed SERDES in house development. Company strives for continual innovation and the...www.asmedia.com.tw
the baseline for the chip is the "1 to 2 port wonder" iPad Pro , but at some point they go past just two ports needed.
[ Thunderbolt needs USB 2.0 port provisioning also separate from the TB controller. ]
What the M1 doesn't have is anything like a x4 , or x8 , x16 PCI-e v4 lane allocation. But a couple of x1's and/or x2's are likely there. There are some NAND chip paths but the SSD controller is inside the M1 and there are no SSD NAND modules in the mix here at all either.
PCi-e . And yes they are needed for ports. The SoC doesn't handle all of them directly. That keeps the pin fan-out down on the SoC itself since it is space constrained for iPad Pro logic board placement. And that most of the SoC's system placements don't need > 2 ports.
Is that going to help with dreams of a future 3rd party x4 PCI-e v4 SSD ? Nope. But it is isn't zero either.
I completely understand and agree. It’s a good reason to have desktops and laptops at varying price and performance available for purchase ?