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TSMC Struggling to Make Enough 3-Nanometer Chips for Apple
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Misleading article, as the yields are better at the outset than they were with the 5nm startup, where TSMC went from a 50% yield to an 80% yield within a month.
Expect that to happen also.
Still believe this is more about shifting M2 inventory than any real shortage, as Apple would know from the 5nm experience that yields at the outset would be around 50% where in fact they exceed that for the 3nm at 55%.
So the 3nm is already better yield than the 5nm at this stage so expect a ramp up in yields and again Apple would know this.
Expect that to happen also.
Still believe this is more about shifting M2 inventory than any real shortage, as Apple would know from the 5nm experience that yields at the outset would be around 50% where in fact they exceed that for the 3nm at 55%.
So the 3nm is already better yield than the 5nm at this stage so expect a ramp up in yields and again Apple would know this.
So what will keep moore’s law alive, Chiplets? There’s the UCIe initiative, universal chiplet interconnect.
but Apple work up the chips from the base M[n] chip in MBA to Pro/Max in MBP to Max/Ultra in the Mac Studio. Mac Pro will start with a with Max or Ultra (or Extreme) if Studio starts at Max. Either they use M2 Ultra or M2 Extreme or wait it out for another three years…
one month ramp to 80% yield is very optimistic for M3, I think.
M1 had a lot more momentum behind it when it was finally released.
"So what will keep moore’s law alive, Chiplets?"
Perhaps this:
Perhaps this:
The switch made from a single molecule
The switch made from a single molecule
Researchers have demonstrated a switch, analogous to a transistor, made from a single molecule called fullerene. By using a carefully tuned laser pulse, the researchers are able to use fullerene to switch the path of an incoming electron in a predictable way. This switching process can be three...
www.sciencedaily.com
lol yep, that stuff ain't cheap. but its necessary since silicon lacks the physical property to keep the electrons within lane after a certain point.
It's all marketing. There are no transistors that are actually 3nm. It's made up marketingspeak. The world is entirely marketing BS.
According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.
I guess it would be really hard to make small, complex devices when you have to keep looking over your shoulder for an impending invasion. 😂
If Apple has the deal outlined in the EE Times article
" ...
Apple will pay TSMC for known good die rather than standard wafer prices, at least for the first three to four quarters of the N3 ramp as yields climb to around 70%, .....
“We think TSMC will move to normal wafer-based pricing on N3 with Apple during the first half of 2024, ..."
Then very probably not. The "high margin" factor (really 'extremely high margin" ) is critical in paying for the all the bad dies that pop out of the early process. If Apple isn't paying for them, it is very, very unlikely that TSMC is going to pay. TSMC would be loosing money paying for around 4x smaller , bad A17 dies . Not a good chance at all that they would be will to eat losses for Apple while Apple pockets all the money that could have paid for them. If Apple was having break even 'problems' with the A17, then perhaps TSMC makes it easier to share the loss load (and make it up later once Apple shifts back up to paying for whole wafers later. )
Also somewhat explains earlier rumor that production capacity was going to 45K wafers per month, but Apple was only using 50% of that to product wafers. If it is TSMC that is pragmatically paying the wafer costs then they have a very high contributing control over how many wafers are processed ( idle equipment costs money , but processed wafers that nobody is paying for probably costs more... the equipment still isn't being paid for and have material costs on top! ). TSMC will 'eat' the bad dies , but very likely only at a "cost/pain" pace they can sustain since there is no revenue to cover the costs.
If Apple is paying for the wafers with a thinner margin die very similar issue. If Apple canceled the "extreme" because thought it wouldn't sell well in a shifting economy where budgets are getting tighter and would only be selling into a subset of the old Mac Pro user base. It isn't a 'no brainer' . It has substantive risk to it. Apple could have a split deal where the A17 and M3 were on that 'good die only' deal and the Mac Pro stuff was on a normal 'pay by wafer' deal. It would be a smaller deal so could fall off the radar of the analysts tracking the 'big money'. But someone at Apple would have be willing to back that move. ( I'm sure TSMC would be happy to take the full price for the wafer. )
This 4 months "bake time" is an issue though. The lead time to do the A17 ramp is going to need to be pushed further back earlier into 2023 ( if need a giant pile of launch dies in July-August have to have to at least started the wafers in March-April if not sooner. ) . And 'pipe cleaner' has to complete several cycles to actually produce the feedback to clean the pipe. If Apple didn't start pushing Mac Pro dies through in July-August there is little chance have had multiple chances for feedback cycle to complete. ( July - October (4 mo) , November - Feb ( 4 mo) would be two. as opposed to December - March (4 mo) would be just one. Wouldn't be until around July that would have two complete cycles with a December first iteration at scale. Wafers were being done in the 'at risk' (pre-high volume manufacturing) phase. It is somewhat a matter of how many did Apple push for.
If there is actually no time for a pipe cleaner of either size to deliver feedback in time for the arbitrary ( in technology terms) bulk July/August build for fixed in stone September annual phone deadline, then would just need to start with A17 just on 'fixed in stone' deadline constraint with no real pipe cleaner at all. Just go and cross fingers will have large enough pile 8 months from then. Not really any time for the A17 to pipe clean to make a M3 Mac Pro SoC either as timely delivered system. The core issue whether Apple wants to pay money to bring the timeline of the Mac Pro launch in or not if it is tightly coupled to N3.
Task-specific accelerators are likely to give the greatest speed and efficiency boosts in the near future.
0.1nm (or 1 Angstroem) would mean you have a thickness of just 1 atom. Usually you need 3 layer to make it stable.
Nothing. It’s dead.
Look here for the advances that 5N to 3N brings at TSMC, roughly a 60% improvement in logic density, BUT no improvement in either SRAM or I/O, resulting in a 30 % improvement in density for what TAMC deems a typical SoC with half its area devoted to logic.
And when the shift comes to 2N (TSMC:s first GAA node) that will according to TSMCs slides bring 15% speed or 25% power savings, at a 10% (!) increase in density.
Aggregate density improvement from 5N to 2N for logic is 1.6x1.1=1.76. Real world including SRAM and I/O, we are looking at roughly 40% more gates in the same area. In six years!
And there is nothing on the horizon that promises that this dog slow pace of progression will accelerate in the future. IMEC estimated an aggregate factor of three improvement until 2038 if all their predictions a) came true and b) on projected schedule. (Which also requires more complex processing which in itself may hamper development as cost doesn’t scale nicely.)
Moore’s law is dead. Really, really dead. There might be an interesting discussion to be had about what this will mean to the huge industry that was built by hitching their wagons to the exponential density growth that lithography provided, but sticking ones head in the sand and denying reality (which I see in forums where people have a vested interest in business as usual) is folly.
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Now they’re going to stay on the real axis and not introduce complex numbers into the mix.
If you add chiplets, especially in the 3rd dimension, you increase silicon density per unit area. I think chiplets are part of the future of Silicon. Otherwise, why create the UCIe?
I would really appreciate if everybody here could not rush out and buy devices with a 3nm chip, and lower the demand, so that way I can easily get 2 iPhone 15 Pros for me and my wife, an M3 MacBook Air and an M3 iPad Pro because that is my current plan
Not yet. 3D integration is just getting off the ground. Have a look at the International Roadmap for Devices and Systems. There is still a lot of room for innovation to keep densities going up.
During the preparation of the 2013 ITRS it was also assessed that horizontal (2D) features were going to be approaching the range of a few nanometers shortly beyond 2020 (Figure ES43) and so it became clear that the semiconductor industry was going to be running out of horizontal space by then! The question was: “Which products were going to be reaching these 2D limits first?” Memory products have always been the leaders in transistor density (i.e., smallest feature pitch) and so it should not have been surprising to realize that the solution to this problem was to come first from companies producing Flash memories. In fact, multiple companies announced in 2014 that future products were going to fully utilize the vertical dimension (Figure ES44). This is not too dissimilar from the approach taken in Manhattan, Tokyo, Hong Kong, or similarly highly crowded places to deal with space limitations: skyscrapers have become the standard approach to maximize “packing density”. In addition, the rapid increase in the number of transistors (i.e., 2/2-years) and the comparably rapid increase in operating frequency throughout the 80s and 90s drove the power dissipation of microprocessors way beyond the 100 W by the 2003−2005 timeframe. This implied that number of transistors and frequency could no longer simultaneously increase. Under these conditions the electronics industry decided to convert to a multicore architecture, and continued to increase the number of transistors at historical rate but limited the operating frequency to few gigahertz. All the above considerations indicated that the structure of integrated circuits needed to evolve from 2D to 3D structures and transistor design needed to be aimed at reduced power consumption as opposed to be optimized for maximum operating frequency.
After 2031 there is no room for 2D geometry scaling, where 3D very large scale integration (VLSI) of circuits and systems using sequential/stacked integration approaches will be necessary.
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Won't delay them in the US! Worst comes to worst, may delay their rollout to other countries...
If it's not "Apple is doomed because they can't produce enough" it's "Apple is doomed because they produced too much"...
Impressively short for 3nm - there are so many more steps to fab a wafer at 3nm than 10nm and larger, and a typical fab cycle at those larger process nodes is in the 10-12 weeks range if not mixed signal too much.
