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Nope I can set them all to 50, until I get to the 4th then it ends..

From what I've been reading this is normal for p67 gigabyte motherboards

I hope I'm not stuck with a trigger, So I'll do some more research over the weekend

Now try what I recommended above on April 7th to the extent that you can now change 3 of them. Then bench them with GB 2 and CB 11.5 and let me know what happens. I suspect that there's a combo which will allow you to achieve a GB 2 score of 20,000+ with lower Vcore that you used to get to the high 17,000s. The lower you can set that base frequency multiplier while keeping turbo staggered high, the better.
 
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Now try what I recommended above on April 7th to the extent that you can now change 3 of them. Then bench them with GB 2 and CB 11.5 and let me know what happens. I suspect that there's a combo which will allow you to achieve a GB 2 score of 20,000+ with lower Vcore that you used to get to the high 17,000s. The lower you can set that base frequency multiplier while keeping turbo staggered high, the better.

I did. at first it wouldn't boot..so I backed the clocks off and ands tried again..got 12000ish in GeekBench.

I changed BLCK to 102.5, 48 multiplier, 1.36v, LLC off and speed step on..

17900 GeekBench added a frame to Cinebench and seemed to be ok, but it's stress testing now..

I'm at the far end of my cooling though even with push/pull on the Cooler Master it's in the high 80's low 90's. I think next week I'll pick up and H80, push/pull the rad unless you know of a better cooler and push back on to a 50multi.

I don't think I'll see 20,000 but I do expect 19,000 or so, not bad for a couple hundred dollar chip. :D
 
I did. at first it wouldn't boot..so I backed the clocks off and ands tried again..got 12000ish in GeekBench.

I changed BLCK to 102.5, 48 multiplier, 1.36v, LLC off and speed step on..

17900 GeekBench added a frame to Cinebench and seemed to be ok, but it's stress testing now..

I'm at the far end of my cooling though even with push/pull on the Cooler Master it's in the high 80's low 90's. I think next week I'll pick up and H80, push/pull the rad unless you know of a better cooler and push back on to a 50multi.

I don't think I'll see 20,000 but I do expect 19,000 or so, not bad for a couple hundred dollar chip. :D

It is important that your system have native power-management activated. You can check whether your system has native power-management activated by watching the boot display when booting in verbose mode (-v) or by examining the native power-management ratios by using the Console.app in the folder - Applications/Utilities/. Run Console and on the left hand side window start to scroll down and click on each kernel.log file and type "ratio" in the search window after each kernel.log file is selected. Here's what my search shows, in part:
...
Mar 18 20:34:16 localhost kernel[0]: IOAPIC: Version 0x20 Vectors 64:87
Mar 18 20:34:16 localhost kernel[0]: ACPI: System State [S0 S3 S4 S5] (S3)
Mar 18 20:34:16 localhost kernel[0]: IOAPIC: Version 0x20 Vectors 88:111
Mar 18 20:34:16 localhost kernel[0]: RTC: Only single RAM bank (128 bytes)
Mar 18 20:34:16 localhost kernel[0]: AppleIntelCPUPowerManagement: Turbo Ratios DDDDEE
Mar 18 20:34:16 localhost kernel[0]: AppleIntelCPUPowerManagement: initialization complete

Mar 18 20:34:16 localhost kernel[0]: mbinit: done (128 MB memory set for mbuf pool)
Mar 18 20:34:16 localhost kernel[0]: From path: "uuid",
Mar 18 20:34:16 localhost kernel[0]: Waiting for boot volume with UUID XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX (Actual no. not revealed by Tutor)
Mar 18 20:34:16 localhost kernel[0]: Waiting on <dict ID="0"><key>IOProviderClass</key><string ID="1">IOResources</string><key>IOResourceMatch</key><string ID="2">boot-uuid-media</string></dict>
Mar 18 20:34:16 localhost kernel[0]: FakeSMC: Opensource SMC device emulator by netkas (C) 2009
Mar 18 20:34:16 localhost kernel[0]: FakeSMC: Monitoring plugins support by mozodojo (C) 2010
Mar 18 20:34:16 localhost kernel[0]: FakeSMC: Original idea of plugins and code sample by usr-sse2 (C) 2010
...

You might try the following (which is the key to the performance boost that SR2Mac and I have experienced on the EVGA SR2 mono) if your system is not experiencing very large turbo ratios:
1) Make sure that ACPI/HPET are enabled - ACPI config or similar title:choose "s3" and under chipset config or similar title choose "High Precision Event Timer" (HPET);
2) Make sure that you have a DSDT.aml file that activates native power-management?
3) Make the appropriate changes to info.plist in FakeSMC.kext as set forth in post #'s 53-57, above;
4) Delete NullCPUPower Management.kext if you have it installed;
5) Make sure that org.chameleon.Boot.plist (Lion) or smbios.plist(SL) (in your Extra folder) does not have any references to either 3,1 or 4,1 by changing them to 5,1 . Also, make sure that the following settings are in the contents of org.chameleon.Boot.plist (but only after having stored an unmodified, backup copy of org.chameleon.Boot.plist elsewhere); then save the change(s), if any:
<key>DSDT</key>
<string>/Extra/DSDT.aml</string>
<key>ForceHPET</key>
<string>No</string>
<key>GenerateCStates</key>
<string>No</string>
<key>GeneratePStates</key>
<string>No</string>
6) Rebuild boot cache.
7) Test with CB 11.5 and GB 2.
 
Hey Chris,

Just wondering, are you still hitting temps around 90C? Let me know... Later... :)
 
Today, Apple released the best Mac Pros its ever released and for lower prices. Some at this forum believe that the effort was too little too late. How well these updates will be received by the larger consuming public is anybody's guess, but I predict that Apple will now sell more Mac Pros over any given unit of time than in the past, just not to real pros who have a true need for maximum performance. This slight update could be Apple's biggest step towards consumerizing its line of trucks - the Mac Pro or it could be a parachut drop over the abyss.
 
Today, Apple released the best Mac Pros its ever released and for lower prices. Some at this forum believe that the effort was too little too late. How well these updates will be received by the larger consuming public is anybody's guess, but I predict that Apple will now sell more Mac Pros over any given unit of time than in the past, just not to real pros who have a true need for maximum performance. This slight update could be Apple's biggest step towards consumerizing its line of trucks - the Mac Pro or it could be a parachut drop over the abyss.


Well from the pricing that I put together for a comparable unit that we have (with the SR-2 setup), the new Mac Pro has gone from $10,750 to now $9,849 (a $900 price break). Yeah, it's got a boost in performance in it's CPUs but not by much and I don't think it'll break the GB 30,000 point barrier. If it does it really should by now for a machine that for over 2 years is hitting GB scores of only 24,000. The new Mac Pros should be hitting GB scores of over 45,000+ at this point.

Your machine is still the GB TOP Dual CPU Mac OS X contender at 40,000+ and it looks like it will stay that way for another 2 years until Apple comes out with another Mac Pro (2 years from now) that can top your SR-2 setup. I'm still hoping soon that I too can reach the same GB scores that you have and top my 34,000+ current score. But for now I just got to get the thing over 27,692 (as a result of replacing all my parts). At around $3,500 spent on our current SR-2 setup that's not too shabby for a machine that can hold it's own compared to a Mac Pro that still near $10,000; even the current new one that's out now, but that's all thanks to you Tutor for your contributions in your continued help to push us further. THANK YOU !!! :cool:
 
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So I got a bit bored today and installed a Gigabyte Z77-D3H motherboard..

I haven't figured out how to overclock it yet (it locks at 1.6 if you touch the frequencies) it runs nice an quiet stock..the interesting part is stock on my previous P67-D3-B3 the GB 64bit was 12,100ish stock on the Z77 board is 13,500ish.

I know this isn't really relevant to Tutor and SR2 but it's obviously a nice upgrade for us i5/i7 types.

Judging by this turn of events I should be able to but into 19,000 @ 5Ghz when the overclocking comes back.

When Apple finally pops their collective head out of their rear the real new MP should be a true beast with these newer chipsets.
 
w3680 & GA-X58A-UD7 rev.1 performance increase

Hello Tutor,

I have recently finished building my first Hackintosh. I'd like to thank PunkNugget for all his help!

My system is getting a geek bench score on 64 bit of 15,300, while my existing iMac gets 12,000. I am pretty sure I should see a greater difference and better performance with the new system.

This is what I have,
1. GA-X58A-UD7 rev. 1 - http://www.ebay.com/itm/25106389818...X:IT&_trksid=p3984.m1497.l2649#ht_1909wt_1156
2. Corsair Dominator 24 GB PC3-12800 1600mHz - http://www.amazon.com/gp/product/B004JPMOVU/ref=oh_details_o03_s00_i00
3. Xeon W3680 - http://www.amazon.com/gp/product/B003EM0T4I/ref=oh_details_o05_s00_i00
4. As my boot - 240GB Mercury EXTREME™ Pro 6G SSD - http://eshop.macsales.com/item/OWC/SSDMX6G240T/
5. XFX AMD Radeon HD 6870 - http://www.amazon.com/gp/product/B004O0OKXK/ref=oh_details_o06_s00_i00
I am cooling with the Corsair H100 - http://www.amazon.com/gp/product/B0051U7HMS/ref=oh_details_o06_s00_i00 as well as cooling with a series of Kaze fans - http://www.amazon.com/gp/product/B001JKNMBE/ref=oh_details_o00_s00_i00

How can I tweak my system as well as under-clock/ over-clock the cpu?
What GB scores should I be expecting?

Thanks so much Tutor,

- HHC
 
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Hello Tutor,

I have recently finished building my first Hackintosh. I'd like to thank PunkNugget for all his help!

My system is getting a geek bench score on 64 bit of 15,300, while my existing iMac gets 12,000. I am pretty sure I should see a greater difference and better performance with the new system.

This is what I have,
1. GA-X58A-UD7 rev. 1 - http://www.ebay.com/itm/25106389818...X:IT&_trksid=p3984.m1497.l2649#ht_1909wt_1156
2. Corsair Dominator 24 GB PC3-12800 1600mHz - http://www.amazon.com/gp/product/B004JPMOVU/ref=oh_details_o03_s00_i00
3. Xeon W3680 - http://www.amazon.com/gp/product/B003EM0T4I/ref=oh_details_o05_s00_i00
4. As my boot - 240GB Mercury EXTREME™ Pro 6G SSD - http://eshop.macsales.com/item/OWC/SSDMX6G240T/
5. XFX AMD Radeon HD 6870 - http://www.amazon.com/gp/product/B004O0OKXK/ref=oh_details_o06_s00_i00
I am cooling with the Corsair H100 - http://www.amazon.com/gp/product/B0051U7HMS/ref=oh_details_o06_s00_i00 as well as cooling with a series of Kaze fans - http://www.amazon.com/gp/product/B001JKNMBE/ref=oh_details_o00_s00_i00

How can I tweak my system as well as under-clock/ over-clock the cpu?
What GB scores should I be expecting?

Thanks so much Tutor,

- HHC

Underclocking should yield a Geekbench 2 score in excess of 20,000. Do you have the proper DSDT file for your CPU?
 
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Underclocking should yield a Geekbench 2 score in excess of 20,000. Do you have the proper DSDT file for your CPU?

Tutor,

That's great news! I don't have a DSDT file, in fact I am don't even know what you are referring to. Wow, that's embarrassing!

I now see on tonyx that there are several for my board but I will need to know a specific f#.
How can I find this f# for my board?
Once I have the file, what will I do with it?

Thank you so much,

- HHC
 
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Tutor,

That's great news! I don't have a DSDT file, in fact I am don't even know what you are referring to. Wow, that's embarrassing!

I now see on tonyx that there are several for my board but I will need to know a specific f#.
How can I find this f# for my board?
Once I have the file, what will I do with it?

Thank you so much,

- HHC

I just booted into my BIOS and can see my BIOS version is FB. Which I found odd since that is a rev.2 BIOS version. I now realize that the rev.1 board I bought is actually a rev.2, rats. Oh well, it's what I have so I will continue with it.

I can upgrade my BIOS from gigabyte to a beta BIOS version or to the stable FC version.
Which one should I do?
Once I decide on the upgrade, which DSDT file should I get?
What will I do with that file?

Since I have a rev2 board and not a rev1 do you still think I can get good performance out of my system?

Thanks,

- Scott
 
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I just booted into my BIOS and can see my BIOS version is FB. Which I found odd since that is a rev.2 BIOS version. I now realize that the rev.1 board I bought is actually a rev.2, rats. Oh well, it's what I have so I will continue with it.

I can upgrade my BIOS from gigabyte to a beta BIOS version or to the stable FC version.
Which one should I do?
Once I decide on the upgrade, which DSDT file should I get?
What will I do with that file?

Since I have a rev2 board and not a rev1 do you still think I can get good performance out of my system?

Thanks,

- Scott

Don't worry about the BIOS "upgrade" yet. I did that on my SR-2 and did more harm than good and what really needed to happen was for me to go back a few revisions on the BIOS on that mobo. Just stick with what's on there now. IF problems occur later (and that's a big IF), then that could be an option. For now just wait until Tutor provides more input. This is a process and I'll be learning (again) as well. Just let him know the current DSDT file you currently have in your Extra folder in your main boot drive. It should say DSDT.aml and another one that I have in there as well is called: dsdt.aml.bk. You may have the same files. If you only have the one that's fine. Just let him know. Later... :)
 
Don't worry about the BIOS "upgrade" yet. I did that on my SR-2 and did more harm than good and what really needed to happen was for me to go back a few revisions on the BIOS on that mobo. Just stick with what's on there now. IF problems occur later (and that's a big IF), then that could be an option. For now just wait until Tutor provides more input. This is a process and I'll be learning (again) as well. Just let him know the current DSDT file you currently have in your Extra folder in your main boot drive. It should say DSDT.aml and another one that I have in there as well is called: dsdt.aml.bk. You may have the same files. If you only have the one that's fine. Just let him know. Later... :)

Thanks SR2Mac,

I appreciate the heads up on the BIOS update. I have attached a couple of shots of my extra folder. I am not sure which DSDT File I have. BTW, I used http://www.kakewalk.se/ to complete my installation.

Do the photos tell you anything?

Thanks,

- HHC
 

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Thanks SR2Mac,

I appreciate the heads up on the BIOS update. I have attached a couple of shots of my extra folder. I am not sure which DSDT File I have. BTW, I used http://www.kakewalk.se/ to complete my installation.

Do the photos tell you anything?

Thanks,

- HHC

Thanks SR2Mac for lending a hand - please continue whenever you see the need. These are matters that benefit from your fresh perspective and input.

hisheartscry, we need to make sure that your system's nativepowermanagement is functioning and recognizing all of your CPU's cores. Please tell me what your system shows for AppleIntelCPUPowerManagement: Turbo Ratios [this is what you need to describe to me].
Here's two ways to do that, namely, by entering verbose mode or by using the console app:

I. Verbose (talkative) Mode - Shows you just what is going on behind the scenes when that normally gray screen displays a spinning icon.
You can boot any recent Mac (and a Hack) in verbose mode by doing this:
1. Shut down your system if it is on.
2. Restart the computer.
3. Immediately press and hold the Command (Apple) key and simultaneously hold down the "v" key for verbose mode. (Command-V) (on a hack perform this step immediately when your Chameleon or other boot loader takes over - this is after your system's summary bios information has been displayed, but I am not suggesting that you press any key to enter bios adjustment mode).
Once you have successfully entered verbose mode, you see white text appear on the screen.
Verbose mode exits automatically when the computer's startup process progresses sufficiently and the blue screen appears. When I did this on my dual 6-core 2009 Mac Pro, it showed "111122" initially for the turbo ratio of one of the 6-cores. It's the same for both CPUs on a dual CPU system. See pic in my post# 29, above, to see the important part of what I now see in verbose mode. In fact, you should read all of the prior posts to ease this process.

OR

II. Check using the Console.app
Check whether nativepowermanagement ratios have been assigned, using the Console.app in the folder - Applications/Utilities/. Run Console and on the left hand side window start to scroll down and click on each kernel.log file and type "ratio" in the search window after each kernel.log file is selected. Here's what my search would have shown initially, in part:
...
Mar 18 20:34:16 localhost kernel[0]: IOAPIC: Version 0x20 Vectors 64:87
Mar 18 20:34:16 localhost kernel[0]: ACPI: System State [S0 S3 S4 S5] (S3)
Mar 18 20:34:16 localhost kernel[0]: IOAPIC: Version 0x20 Vectors 88:111
Mar 18 20:34:16 localhost kernel[0]: RTC: Only single RAM bank (128 bytes)
Mar 18 20:34:16 localhost kernel[0]: AppleIntelCPUPowerManagement: Turbo Ratios 111122
Mar 18 20:34:16 localhost kernel[0]: AppleIntelCPUPowerManagement: initialization complete
Mar 18 20:34:16 localhost kernel[0]: mbinit: done (128 MB memory set for mbuf pool)
Mar 18 20:34:16 localhost kernel[0]: From path: "uuid",
Mar 18 20:34:16 localhost kernel[0]: Waiting for boot volume with UUID XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX (Actual no. not revealed by Tutor)
Mar 18 20:34:16 localhost kernel[0]: Waiting on <dict ID="0"><key>IOProviderClass</key><string ID="1">IOResources</string><key>IOResourceMatch</key><string ID="2">boot-uuid-media</string></dict>
Mar 18 20:34:16 localhost kernel[0]: FakeSMC: Opensource SMC device emulator by netkas (C) 2009
Mar 18 20:34:16 localhost kernel[0]: FakeSMC: Monitoring plugins support by mozodojo (C) 2010
Mar 18 20:34:16 localhost kernel[0]: FakeSMC: Original idea of plugins and code sample by usr-sse2 (C) 2010
...

I underlined the important information that you need to give to me because we need to make sure that you nativepowermanagement is functioning and recognizing all of your CPUs cores.

Get Plistedit Pro from FatCat - Google the underlined text or go to http://www.fatcatsoftware.com/plisteditpro/ . Get the demo for now, but I highly recommend that you purchase it - you'll often regret it if you don't. Read the info re it on Fatcat's site. We'll soon put it to use.

BTW - I always boot in verbose mode. On the Mac, just use Plistedit Pro to edit the file com.apple.Boot.plist located in L/P/SC (Library/Preferences/SystemConfiguration), to read as follows:

<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
<plist version="1.0">
<dict>
<key>Kernel Flags</key>
<string>arch=x86_64 -v</string>
</dict>
</plist>


The same type of change can be given on a Hack by editing the file com.apple.Boot.plist in the Extra folder at the root level of your HD by only adding "-v" as shown above.
 
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I had a little trouble booting in verbose mode, i kept hanging with a flashing cursor at 89%...so I used the console.app.
I only saw 2 kernel.log files and this is what they listed:

Kernal.log under "files":
Jun 15 06:33:16 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 06:33:16 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 06:33:16 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 07:56:29 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 07:56:29 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 07:56:29 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 32 ]
Jun 15 08:30:19 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 08:30:19 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 08:30:19 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 32 ]
Jun 15 09:03:11 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:03:11 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:03:11 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:07:51 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:07:51 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:07:51 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:10:05 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:10:05 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:10:05 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:11:55 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:11:55 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:11:55 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:18:30 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:18:30 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:18:30 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 10:09:53 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 10:09:53 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 10:09:53 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 10:51:17 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 10:51:17 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 10:51:17 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 11:15:15 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 11:15:15 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 11:15:15 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 11:19:22 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 11:19:22 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 11:19:22 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 11:32:18 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 11:32:18 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 11:32:18 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 12:03:07 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 12:03:07 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 12:03:07 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 08:53:30 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 08:53:30 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 08:53:30 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 09:20:24 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 09:20:24 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 09:20:24 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 09:24:16 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 09:24:16 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 09:24:16 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 09:39:49 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 09:39:49 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 09:39:49 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 10:23:04 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 10:23:04 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 10:23:04 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 10:40:38 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 10:40:38 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 10:40:38 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 12:58:17 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 12:58:17 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 12:58:17 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:09:22 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:09:22 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:09:22 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:24:42 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:24:42 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:24:42 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:29:37 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:29:37 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:29:37 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:40:16 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:40:16 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:40:16 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 14:18:36 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 14:18:36 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 14:18:36 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 15:04:31 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 15:04:31 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 15:04:31 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 18:54:38 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 18:54:38 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 18:54:38 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 19:15:49 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 19:15:49 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 19:15:49 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:08:34 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:08:34 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:08:34 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:16:08 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:16:08 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:16:08 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:20:57 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:20:57 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:20:57 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:26:34 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:26:34 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:26:34 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 23:27:13 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 23:27:13 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 23:27:13 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 07:53:38 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 07:53:38 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 07:53:38 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 13:09:09 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 13:09:09 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 13:09:09 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 13:11:08 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 13:11:08 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 13:11:08 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 13:13:06 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 13:13:06 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 13:13:06 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]

Kernal.log under "/var/log":
Jun 15 06:33:16 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 06:33:16 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 06:33:16 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 07:56:29 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 07:56:29 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 07:56:29 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 32 ]
Jun 15 08:30:19 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 08:30:19 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 08:30:19 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 32 ]
Jun 15 09:03:11 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:03:11 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:03:11 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:07:51 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:07:51 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:07:51 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:10:05 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:10:05 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:10:05 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:11:55 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:11:55 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:11:55 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 09:18:30 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 09:18:30 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 09:18:30 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 10:09:53 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 10:09:53 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 10:09:53 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 10:51:17 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 10:51:17 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 10:51:17 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 11:15:15 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 11:15:15 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 11:15:15 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 11:19:22 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 11:19:22 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 11:19:22 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 11:32:18 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 11:32:18 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 11:32:18 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 15 12:03:07 localhost kernel[0]: [ PCI configuration begin ]
Jun 15 12:03:07 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 15 12:03:07 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 08:53:30 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 08:53:30 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 08:53:30 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 09:20:24 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 09:20:24 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 09:20:24 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 09:24:16 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 09:24:16 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 09:24:16 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 09:39:49 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 09:39:49 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 09:39:49 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 10:23:04 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 10:23:04 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 10:23:04 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 10:40:38 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 10:40:38 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 10:40:38 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 12:58:17 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 12:58:17 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 12:58:17 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:09:22 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:09:22 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:09:22 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:24:42 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:24:42 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:24:42 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:29:37 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:29:37 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:29:37 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 13:40:16 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 13:40:16 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 13:40:16 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 14:18:36 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 14:18:36 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 14:18:36 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 15:04:31 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 15:04:31 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 15:04:31 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 18:54:38 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 18:54:38 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 18:54:38 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 19:15:49 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 19:15:49 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 19:15:49 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:08:34 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:08:34 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:08:34 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:16:08 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:16:08 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:16:08 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:20:57 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:20:57 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:20:57 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 20:26:34 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 20:26:34 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 20:26:34 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 16 23:27:13 localhost kernel[0]: [ PCI configuration begin ]
Jun 16 23:27:13 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 16 23:27:13 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 07:53:38 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 07:53:38 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 07:53:38 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 13:09:09 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 13:09:09 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 13:09:09 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 13:11:08 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 13:11:08 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 13:11:08 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]
Jun 17 13:13:06 localhost kernel[0]: [ PCI configuration begin ]
Jun 17 13:13:06 localhost kernel[0]: PCI configuration changed (bridge=4 device=3 cardbus=0)
Jun 17 13:13:06 localhost kernel[0]: [ PCI configuration end, bridges 10 devices 31 ]


I don't see "Turbo Ratios"

...also I just bought Plistedit Pro,

Thanks so much for your help,

- HHC
 
Last edited:
I just confirmed in the BIOS and yes Turbo is enabled. Everything on the Advanced CPU core features page is enabled.

- HHC

BTW - I always boot in verbose mode. On the Mac, just use Plistedit Pro to edit the file com.apple.Boot.plist located in L/P/SC (Library/Preferences/SystemConfiguration), to read as follows:

<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
<plist version="1.0">
<dict>
<key>Kernel Flags</key>
<string>arch=x86_64 -v</string>
</dict>
</plist>


The same type of change can be given on a Hack by editing the file com.apple.Boot.plist in the Extra folder at the root level of your HD by only adding "-v" as shown above. Try to spot the ratios while booting using this method. Also,

1) Make sure that ACPI/HPET are enabled - Power Management menu on main bios screen/ACPI Config/General *choose s3 and Under Chipset Config choose High Precision Event Timer (HPET);
2) Enable C-states in bios.
3) Make the appropriate changes to info.plist in FakeSMC.kext as set forth in post #'s 53-57, above;
4) Delete NullCPUPower Management.kext if you have it installed;
5) Make sure that org.chameleon.Boot.plist (Lion) or smbios.plist(SL) (in your Extra folder) does not have any references to either 3,1 or 4,1 by changing them to 5,1 . Also, make sure that the following settings are in the contents of org.chameleon.Boot.plist after having stored an unmodified copy of org.chameleon.Boot.plist to that file that you create and name "UseOnlyIfNeeded" folder; then save the change:
<key>DSDT</key>
<string>/Extra/DSDT.aml</string>
<key>ForceHPET</key>
<string>No</string>
<key>GenerateCStates</key>
<string>No</string>
<key>GeneratePStates</key>
<string>No</string>
6) Rebuild boot cache.
 
Last edited:
BTW - I always boot in verbose mode. On the Mac, just use Plistedit Pro to edit the file com.apple.Boot.plist located in L/P/SC (Library/Preferences/SystemConfiguration), to read as follows:

<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist PUBLIC "-//Apple//DTD PLIST 1.0//EN" "http://www.apple.com/DTDs/PropertyList-1.0.dtd">
<plist version="1.0">
<dict>
<key>Kernel Flags</key>
<string>arch=x86_64 -v</string>
</dict>
</plist>


The same type of change can be given on a Hack by editing the file com.apple.Boot.plist in the Extra folder at the root level of your HD by only adding "-v" as shown above. Try to spot the ratios while booting using this method.

In my extra folder I have org.chameleon.boot.plist and smbios.plist

WHich one should I edit?

- HHC
 
Keep in mind this rule that applies to my helping others - almost all of the time, I do not have others' motherboards so I do not know what features they have or what they are properly called so I can only be general, at best, but since the board info is displayed before their eyes, they have to be very specific about what they're are seeing then, hopefully, I can figure out what to do. Thanks for understanding my limitations and your advantages.

----------

In my extra folder I have org.chameleon.boot.plist and smbios.plist

WHich one should I edit?

- HHC

Does either of those files have a kernel flag when you open it with Plistedit Pro - it looks like this <key>Kernel Flags</key>
 
Keep in mind this rule that applies to my helping others - almost all of the time, I do not have others' motherboards so I do not know what features they have or what they are properly called so I can only be general, at best, but since the board info is displayed before their eyes, they have to be very specific about what they're are seeing then, hopefully, I can figure out what to do. Thanks for understanding my limitations and your advantages.

----------



Does either of those files have a kernel flag when you open it with Plistedit Pro - it looks like this <key>Kernel Flags</key>

Tutor,

I appreciate you taking time to help me and others...what a huge help!

I did everything you suggested above, and now in the console.app I see
Jun 17 15:08:34 localhost kernel[0]: AppleIntelCPUPowerManagement: Turbo Ratios 111122

Should I now work on ensuring I have the correct DSDT file you mentioned previously?
Once I download it do I simply replace the existing DSDT file?

Thanks so much Tutor,

- Scott
 
....I did everything you suggested above, and now in the console.app I see
Jun 17 15:08:34 localhost kernel[0]: AppleIntelCPUPowerManagement: Turbo Ratios 111122....
Once I download it do I simply replace the existing DSDT file?

Before we change the DSDT file, please make sure that you've done everything that I suggest in post no. 193, above. After that, please send me pics/screen shots of the performance adjustment parameters in your system's bios.
 
I found the manual for your Mobo and read it

This is where you are now:W3680 Factory:

base Frequency = 3333; 3333 / 133 = 25.0601503759399 or 25
turbo Frequency = 3600; 3600 / 133 = 27.0676691729323 or 27
Difference = 1 or 2 bins maxSpec VID is 1.375 for your CPU, according to CPU World. So we'll not exceed that Vcore amount.



This is how we'll first try to get W3680 clocked
MIT = MB Intelligent tweaker main screen


1) Under MIT, set CPU Vcore to one step under 1.375V [ Spec VID is 1.375 for your CPU, according to CPU World. So we'll not exceed that Vcore amount. ]; set CPU Clock Ratio to 34; enable QPI Clock Ratio and set it to x48.
2) Under Advanced CPU Features, set CPU Clock Ratio to 34 and enable all Advanced CPU Features.
3) Under Advanced Clock Control, enable BCLK Control and set BCLK to 125 and enable PCI Frequency and set it to 101.
4) Under Advanced DRAM Features, set Performance Enhance to standard; disable XMP; enable System Memory Multiplier and set it to 12; set DRAM Voltage to 1.65V.
5) On Power Management Setup page, set ACPI Suspend Type to [S3(STR)]; enable HPET support and set HPET mode to 64 bit.
6) On the Integrated Peripherals page, set all CTR Modes, including ICH SATA Control Mode, to ACHI - in other words change IDE to AHCI in every instance;
7) On the CPU Health Status page, enable CPU Warning Temperature and Fan Fail Warning; disable Smart Fan Control; set CPU Smart Fan Control to Auto.
8) Under advanced Voltage Control, set Load Line Calibration to Standard.


The above settings, which you should save and save each variation separately*, should result in the following.
base Frequency = 25 (CPU Clock Ratio) x 125 (BCLK) = 3125 = idle speed
turbo Frequencies Stage 1 = [34 (CPU Clock Ratio) +1 = 35] x 125 (BCLK) = 4.375 GHz
turbo Frequencies Stage 2 = [34 (CPU Clock Ratio) +2 = 36] x 125 (BCLK) = 4.500 GHz
Difference = (10 or A) or (11 or B) bins max; so your CPU ratios would be AAAABB rather than 111122 (check in console or on boot screen in verbose mode "-v").

*/ You may have lower that "34" CPU Clock Ratio somewhat (to 33 or 32) to keep the system stable and or boot. For each step that you lower that figure raise the BCLK by three (e.g., with a CPU Clock ratio of 33 BCLK should be 128 or with a CPU Clock ratio of 32 BCLK should be 131), but keep the BLCK at or below 131 and not lower than 25. Let me know how it goes and how it benches.
 
Last edited:
Before we change the DSDT file, please make sure that you've done everything that I suggest in post no. 193, above. After that, please send me pics/screen shots of the performance adjustment parameters in your system's bios.

I am pretty sure I changed everything...with 2 possible exceptions. I had trouble with:
3) Make the appropriate changes to info.plist in FakeSMC.kext as set forth in post #'s 53-57, above;
- Using the find and replace function I was only able to change "napa". The other wasn't there.
- The sync button was greyed out.

and

4) Delete NullCPUPower Management.kext if you have it installed
I didn't install it but I do see the file in the extensions folder. Does that mean it is installed?
How would I uninstall it?

Thanks again,

- Scott
 
This is where you are now:W3680 Factory:

base Frequency = 3333; 3333 / 133 = 25.0601503759399 or 25
turbo Frequency = 3600; 3600 / 133 = 27.0676691729323 or 27
Difference = 1 or 2 bins maxSpec VID is 1.375 for your CPU, according to CPU World. So we'll not exceed that Vcore amount.



This is how we'll first try to get W3680 clocked
MIT = MB Intelligent tweaker main screen


1) Under MIT, set CPU Vcore to one step under 1.375V [ Spec VID is 1.375 for your CPU, according to CPU World. So we'll not exceed that Vcore amount. ]; set CPU Clock Ratio to 34; enable QPI Clock Ratio and set it to x48.
2) Under Advanced CPU Features, set CPU Clock Ratio to 34 and enable all Advanced CPU Features.
3) Under Advanced Clock Control, enable BCLK Control and set BCLK to 125 and enable PCI Frequency and set it to 101.
4) Under Advanced DRAM Features, set Performance Enhance to standard; disable XMP; enable System Memory Multiplier and set it to 12; set DRAM Voltage to 1.65V.
5) On Power Management Setup page, set ACPI Suspend Type to [S3(STR)]; enable HPET support and set HPET mode to 64 bit.
6) On the Integrated Peripherals page, set all CTR Modes, including ICH SATA Control Mode, to ACHI - in other words change IDE to AHCI in every instance;
7) On the CPU Health Status page, enable CPU Warning Temperature and Fan Fail Warning; disable Smart Fan Control; set CPU Smart Fan Control to Auto.
8) Under advanced Voltage Control, set Load Line Calibration to Standard.


The above settings, which you should save and save each variation separately*, should result in the following.
base Frequency = 25 (CPU Clock Ratio) x 125 (BCLK) = 3125 = idle speed
turbo Frequencies Stage 1 = [34 (CPU Clock Ratio) +1 = 35] x 125 (BCLK) = 4.375 GHz
turbo Frequencies Stage 2 = [34 (CPU Clock Ratio) +2 = 36] x 125 (BCLK) = 4.500 GHz
Difference = (10 or A) or (11 or B) bins max; so your CPU ratios would be AAAABB rather than 111122 (check in console or on boot screen in verbose mode "-v").

*/ You may have lower that "34" CPU Clock Ratio somewhat (to 33 or 32) to keep the system stable and or boot. For each step that you lower that figure raise the BCLK by three (e.g., with a CPU Clock ratio of 33 BCLK should be 128 or with a CPU Clock ratio of 32 BCLK should be 131), but keep the BLCK at or below 131 and not lower than 25. Let me know how it goes and how it benches.

I tried to carefully go through these setting changes...I saved them but now it won't start. The mobo cycles c1 18,26 and c3 then back to c1. Of course I now see you said save each variation separately...lesson learned I guess!

BTW, you suggested I set the set DRAM Voltage to 1.65V...the closest option I had was 1.64V. Hope that was ok.

My amature side wants to panic but I am I am putting on a strong face:)

Any ideas?

Thanks for your time,

- Scott
 
Last edited:
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