AMD said their TSMC N5 node is 'custom' and optimised for HPC. Seems the desktop processors are taking a free ride for performance.
The words Papermaster actually used was a "specialized , N5 , HPC process that enabled additional frequency past the baseline process". It is rather a odd if AMD is using the original N5 fab process at this point. N5 is over two years old at this point. Why would they jump from N6 to a two year old process? TSMC rolls out a couple of letter 'modifier' process specialized increments after the baseline gets stable anyway to their customer base as another option.
There is pretty good chance that this is technically N5P that they are moving to. N5P is over a year old. . So it isn't new either. (no high risk of initial growing pains or too few wafers to go around) N5P get +10% power or +5% performance over the baseline N5 process. So something as simple as just using N5P fits his basic description without going into a zone where only AMD can get it. AMD could easily just skip using the letter adjectives to make a simpler , clearer presentation without going into the weeds of TSMC fab tech.
Also would not be surprising if Zen 4c was on N4P. And that N4P is a small contributor to making the 4c cores smaller. ( 6% isn't huge chunk of a 50% reduction but if can get it for 'close to free' why leave it on the table. Getting 44% is a bit easier. ). 4c arriving closer to June 2023 would make sense as N4P ramping now.
From Papermaster's description of balancing power , area , and high frequency 4c could have a heavy contribution of a library shift that tosses out the high frequency ability and chooses area and power saving options instead. (plus loose some re-write registers and/or cache . Can juggle design libraries, but some part of that 44% is likely just a chunk of something being dropped. ). Can still have the 'add' function, but perhaps not three 'adds' in parallel ability.
N4P takes the same baseline design rules as N5P. And if swapping cell libraries anyway to remove the "turbo" frequency trade-off anyway there is a re-flow design overhead anyway. Adding shift to N4P on top of that isn't going t be that much more expensive. ( And they can probably re-use chunks of this work on a laptop part later ). AMD's roadmap diagram says that Zen 4 family is spread over N5 and N4.
AMD also said their TSMC N6 based new I/O die for clients consumes 20W under load. Hope this settles the speculation.
" ... The new I/O die uses the 6nm process and houses the PCIe 5.0 and DDR5 memory controllers along with a much-needed addition for AMD — the RDNA 2 graphics engine. The new 6nm I/O die also has a low-power architecture based on features pulled in from AMD's
Ryzen 6000 chips, so it has enhanced low power management features and an expanded palette of low-power states. AMD says this chip now consumes around 20W, which is less than it did with Ryzen 5000, and will deliver the majority of the power savings we see in Ryzen 7000.
Surprisingly, the new I/O die appears to be roughly the same size as the previous-gen 12nm I/O die. However, given that the 6nm die is far denser than the 12nm die from GlobalFoundries, meaning it has far more transistors, i."
https://www.tomshardware.com/news/a...ications-pricing-benchmarks-all-we-know-specs
The desktop 7nm tees up the 6nm laptop which sends contributions into the 5nm desktop product. AMD doing a steady set of base hits just to move the products around the bases to get to a 'homerun'. Intel keeps going to the plate and trying exotics stuff to hit some 500ft homerun shot over the center outfield wall. Apple can beat up on Intel from time to time with the strategy they are following. It is going to be lot harder to beat AMD when they are on the same process node with the non-over-reach strategy they are using. Apple is somewhat lucky AMD is mainly trying to build server focused chiplets as opposed to going "all in" on laptop product. But AMD putting laptop SoC last on the priority queue is still getting numerous iterations at this point (at least at the high end of the laptop SoC product line).