Not really. Intel‘s disadvantage stems from the node to only a minor degree. 3nm would help, but not that much
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Intel Alder Lake vs. Apple M1
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Are you sure that the ISA has a more significant influence than the node? According to Anandtech, the TSMC 5nm node needs 30% less power and performs 15% better than the TSMC 7nm node.
TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022
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Well, that sounds about correct. Now, given that Intel‘s got a roughly 4-5x disavantage in terms of performance per watt, moving to 5 nm would of course decrease the gap, but the disadvantage would still be significantAre you sure that the ISA has a more significant influence than the node? According to Anandtech, TSMC 5nm node needs 30% less power and performs 15% better than TSMC 7nm node.
TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022
www.anandtech.com
Are you sure that the ISA has a more significant influence than the node? According to Anandtech, the TSMC 5nm node needs 30% less power and performs 15% better than the TSMC 7nm node.
TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022
Of course you need to compare N7+ to N5 when estimating what happens when Intel moves from 10nm ESF to N5. So relatively minor compared to architectural differences.
I thought I had read that the Intel current node was similar to the TSMC N7. Do you have any link that explains it?
From density perspective they are both very similar. However both Intel and TSMC are doing iterations in order to improve their processes with respect to power/performance characteristics. For TSMC the third iteration is N7+ and for Intel it is 10 ESF aka Intel 7. So if we assume that the 7nm TSMC and 10nm Intel processes are very similar, we would also conclude that their 3rd iteration is sufficiently similar - this still assumes that Intel is 2 years behind TSMC (2019 vs 2021)
The info about the transistor density of the Intel 7 in Wikipedia is not clear. It seems its transistor density is closer to TSMC N7 density (almost 100 MTr / mm²) than to TSMC N7+ density (almost 115 MTr / mm²).
Sources:
10 nm process - Wikipedia
7 nm process - Wikipedia
The info about the transistor density of the Intel 7 in Wikipedia is not clear. It seems its transistor density is closer to TSMC N7 density (almost 100 MTr / mm²) than to TSMC N7+ density (almost 115 MTr / mm²).
Sources:
10 nm process - Wikipedia
en.wikipedia.org
7 nm process - Wikipedia
en.wikipedia.org
Transistors care about their dimensions and the dimensions of the wires they drive (including their height), not their density. If one more person talks about density in comparing nodes I’ll scream.
G’day.
(height is not accounted for in density. Two chips with the same density can have different transistor dimensions because density is a function of minimum transistor sizes plus transistor spacing. Spacing rules are independent of sizing rules.)
1-. Why is transistor density used so much to compare nodes between different companies? For instance, Anandtech:
"Analysts from China Renaissance estimate that TSMC's N5 features a transistor density of around 170 million transistors per square millimeter (MTr/mm2)[...]. By contrast, Samsung's Foundry's 5LPE can boast with about 125 MTr/mm2 ~130 MTr/mm2, whereas Intel's 10 nm features an approximately 100 MTr/mm2 density."
Source: https://www.anandtech.com/show/16639/tsmc-update-2nm-in-development-3nm-4nm-on-track-for-20222-. Is there a better way to compare nodes between companies?
3-. What influences Apple's performance/consumption advantage more: the ISA or the node?
4-. Which TMSC node is closer to Intel 7?
There’s a third point of comparison:
1. Node
2. ISA
3. Microarchitecture
(4. software optimization but we’re going to ignore that for now and assume it is the same here - I think I came up with a 5th earlier but can’t remember and it’s first three we’re concerned with here)
An Arm X1 core and an Apple firestorm core share the same ISA (basically anyway I’m not sure about detail version 8.x and X1 might also support ARM v7 which firestorm does not) but have very different microarchitectures - same with Intel and AMD cores for x86-64.
In terms of how much each matters? Well depending on the test, Apple is ahead of Intel by about 4x in ST and 2.5x in MT with a wide range depending on the test and actual implementation (i9s will have worse perf/W than an i5 for instance).
So Intel has to decrease its single thread perf/W by 75% and multithread by 60%.
Node might account for 20% (very rough estimate)
ISA alone might account for another 10% (from what I can tell an extremely rough estimate, but that’s what’s floating around engineering circles)
The rest is the microarchitecture.
You are making a large assumption that Intel is going to apply TMSC N3 to large monolithic dies. Pretty good chance they are not. Intel's graphics is on leading edge TMSC adoption rate. The Arc A-series GPU are going to come out this 1H 22 at TMSC N6 so something in 2023 at N3 ( especially if it is relatively very small) wouldn't be a big leap to make.
The iGPU doesn't have to be on the same die as the CPU (x86-64) cores. So the move to 3nm may not impact the CPU core performance much. ( may get some more thermal headroom if the iGPU lowers its profile a bit. )
There are two "war fronts" that Intel has to make up ground on in the laptop space. One is CPU cores and the other is on iGPU performance. Pretty good chance that N3 is going to be applied to GPU before it is applied to CPU cores. ( also if don't have the CPU core implementation consuming space the N3 die is even smaller. Which makes it easier to fit in production queue space when Apple is trying to hog most of the capacity. )
The other disconnect is that Intel's "Intel 7" is not the 'old' "Intel 10nm" anymore than the TSMC N6 is N7. It is actually moving. Not super fast , but moving.
The mid-late 2023 iteration from Intel is likely a combo of Intel 4 + TSMC N3 + Intel 7 rather than 100% N3.
Late 2022 an early 2023 is likely their "cleaned up" iteration on Alder Lake. ( where dump the bulky AVX-512 units not using anyway and swap in some more E cores and a minor tweaks on production to get some increment on thermal/clocks. ). That likely will still be monolithic die for CPU+GPU part.
If Intel's ARC GPU product line gets substantive in 2H22 - 1H23 then Intel is probably looking to use al the TSMC allocation they can get on GPUs not CPUs. They have inertia in the CPU package market. They are just trying to carve out a solid place in the discrete GPU one.
Intel can 'Pipeclean" TSMC N3 with their iGPU tile/chiplet and would open the door for the discrete GPU dies to follow later in 2023-24.
The depends upon the size of the dies asking for. If Ask for 30mm2 dies on 300mm wafers has a much higher usable unit count than 130mm2 dies on 300mm wafers.
For example
CALY Technologies
caly-technologies.com
5.4 x 5.6 on a 300mm wafer ---> 1876 good dies
11.2 x 11.7 on a 300mm wafer ---> 386 good dies
That's an order of magnitude improvement in useful dies. Just don't need as many wafers to do the exact same volume. If Intel needed 10x less wafers than Apple did then there is a better chance they can "make do" with a much smaller wafer start allocation.
I’ve seen two rumors: 1) That Meteor Lake will clean up AVX-512 by getting rid of it as you put here. 2) That it will implement an AVX-512 sharing scheme that Intel has patented and allow the E-cores to access AVX-512 units. Either way, the AVX-512 debacle on Alder Lake should indeed get resolved.
David Kanter multi page article (rant ?) about why Transistor count is a flawed metric. (It’s actually pretty good.)
1. I don’t know? Because people don’t know any better?
2. Any time I start working with a fab to figure out what I can do in a chip design I immediately look at:
- minimum feature width, per layer
- number of layers
- minimum spacing per layer
- minimum area, for at least the semiconductor and poly layers
Related is minimum pitch per layer, but if you know width and spacing you have a feel for pitch (though sometimes the minimum pitch is greater than what you would get if you used minimum width and spacing. It’s complicated).
3. It depends. The difference between any two RISC ISAs is likely going to make much less of a difference than process node. The difference between RISC and CISC is likely bigger than the difference between two consecutive process nodes. But if you are 2 process nodes apart, then that would likely have a bigger effect than CISC vs. RISC. But, of course, it all depends. I’m assuming two modern ISA’s intended for the same market segments.
Things like microarchitecture and physical design have an equal effect as well.
4. Intel 7 is what they used to call 10nm? (I no longer keep track). I seem to recall that it had basic design rules that were reasonably close to TSMC 7nm, but just a bit worse. But I don’t have the Intel design rules in front of me.
This is all true. As I’ve said before, CPUs never come close to using the maximum density. What matters is how fast you can toggle a transistor, which is based on its dimensions, its capacitance, and the parasitic impedance of the wires (which is a function of their 3-dimensional dimensions, spacing, and materials).
Yeah I should’ve said “fabrication” rather than “node” since, as you know better than I, that the last time Intel tried to be a foundry for others (when they had a node advantage) it was a disaster because they couldn’t properly communicate design with other companies.
I doubt the "solution" will wait for Meteor Lake. Gen 13 ( Raptor Lake) reportedly doubles the number of 'E' cores. Doing that and dragging around a deactivated AVX-512 makes about zero sense. I think that is way Intel is being so pedantic about turning off AVX-512 on a socket that will be "shared" with the Raport Lake. That hack (even if could get it to work on Alder Lake) won't work anymore later at all.
If "grow" the transistor budget with twice as many E cores then the die would grow bigger ( and cost more ) if kept around that 'dead weight'. Most likely could at least partially 'pay' for those E cores by dumping several AVX-512 units. Even if a net increase in die size it would be less than a cost sink hole. ( It isn't like Intel is going to get higher still prices for the Gen 13. If anything the pricing battle with AMD is just going to get steeper as the chip shortage subsides into 2023. )
Gen 12 (Alder lake ) is a bit of a "rush job" in that the P cores are almost exactly from the Sapphire Rapids ( Xeon next gen) implementation to save time and resources. The 'tangent' that Intel went on with Rocket Lake ( backporting back to 14nm++++++ ) probably cost them resources to do Alder Lake "correctly". Hence have the hack of stuffing server P cores in and then doubling down on the 'e' core bet. There is certainly time to "fix" Raptor Lake cores by simpilying removing function units that are pragmatically not even invoked. That should not take a ton of effort to do a "chop". Waiting until 2023 to do that is more than kind of silly when it really shouldn't have been there in the first place (given the design choices made. I image the AVX-512 folks are not happy with dumping it, but )
Gen 14 is about where they could bring it back ( with some sharing option perhaps). The transistor budget will be much higher ( Intel 4) . AVX-512 will be more affordable. [ And I suspect they will probably back down from the tangent of going 'crazy' on the number of E cores. Gen 13 will be another "stop gap" move that doesn't signal long term direction. Going 'crazy' on E core count is a compensation for being "stuck" on Intel 7 ( 10+++++ ) to cover MT performance gaps. Get back on pace and can make smaller P cores with the fab improvement. ]
Oops, you’re right. That was just me forgetting which name was which I thought it was Meteor then Raptor rather than Raptor then Meteor. But yes it should be cleaned up in the next generation whatever the name.
George Box said: "All models are wrong, but some are useful." I agree that transistor density doesn't reflect the intricacies of chips. But, I believe it is useful to compare nodes because it is a single number.
I find 20% too little, but I may be wrong.
Let's suppose that I manufacture a CPU in TSMC N7, and it gets 100 units of performance and 100 units of consumption. So, the performance/consumption ratio is 1. According to Anandtech, if I use TSMC N5 instead, my new CPU could decrease the consumption by 30% (from 100 to 70) and increase the performance by 15% (from 100 to 115). So, the new performance/consumption ratio would be 115/70 = 1.64. That's much higher than 20%.
Do my simplifications make my model wrong? How?
I thought some microarchitecture optimizations depends on the ISA.
If AMD/Intel could adapt the Firestorm/Icestorm microarchitecture to x64 and use the same TMSC node as Apple to implement it, would the difference be only 10%?
Intel 7 was "Enhanced Super Fin of 10nm" not 10nm. Th enhance super fin is tweaking some of the very same parameters you are highlighting so trying to dump Intel 7 into the same basket as "revised 10nm " starting point ( Ice Lake era ) is wouldn't be correct. And Intel 7 is a more legitimate "relabel".
But it’s a single number that tells me nothing about what happens if I fab the exact same processor on each of those two nodes.
As much as I love that quote, I think according to @cmaier the more relevant one in this context is “lies, damned lies, and statistics” - Benjamin Disraeli (often misattributed to Twain).
Yes you don’t get both the 15 and 30.
According to TSMC themselves: “ N5 technology provides about 20% faster speed than N7 technology or about 40% power reduction.”
5nm Technology - Taiwan Semiconductor Manufacturing Company Limited
TSMC’s 5nm (N5) Fin Field-Effect Transistor (FinFET) technology successfully entered volume production in the second quarter of 2020 and experienced a strong ramp in the second half of 2020.
Intel 7 is also a superior node to Intel 10 - by about 15-20%. So i could be a little low but if Intel 10nm is around TSMC 7, that would place 7 at around N7+ which is roughly 20% worse perf/W than N5.
Yeah my “separate categories” definitely bleed together. Some stuff like especially the decoder are strongly ISA dependent. Some is partially dependent in a downstream knock on like a wider core being easier to achieve on ARM than x86. Other stuff like the physical design straddle fabrication and uarch. People say in general though 90% of what you design in a core has little to do with ISA. The 5th category I couldn’t think of earlier was basically uncore/SOC: memory hierarchy, fabric, comms which especially for multicore and mixed accelerator workloads matters quite a bit. This also bleeds into microarchitecture design like with caches and how those impact how you design a core. So my separate categories are not truly distinct. It’s just easier to categorize them this way.