Two years is a reasonable cadence for a new architecture. The point was Raptor lake is not a new architecture and you’re right I should’ve specified the performance cores of the A15 to A14 as avalanche is a cleaned up firestorm. So Apple and Intel are also both going ~two years between new performance architectures.
@leman and @Andropov aren’t confused. They were simply pointing out that your invocation of big.Little wasn’t accurate in this context. Intel’s version of heterogeneous cores are not conceptually the same as what big.Little was. Perhaps overly pedantic as the rest of your post is fine in this respect, but the better tech reviewers have been careful to distinguish between the two heterogeneous core strategies. If you want to say heterogeneous cores have become the norm that’s fine but big.Little means something specific and that’s not what Intel has built. In fact, technically it’s an ARM ltd marketing term so super pedantically it shouldn’t apply anywhere else but it’s become so ubiquitous that it’s a bit like insisting on calling something sparkling wine at this point. But even with that said, calling what Intel has big.Little is incorrect. It’s heterogeneous, but conceptually not big.Little. Heck there are some who would argue Apple isn’t truly big.Little because Icestorm cores are too powerful! I’d disagree and I’d say the way they’ve been changed from the M1 to the M1 Max/Pro (dropping down to two with potentially double the clock speed depending on the situation) hits home that Apple views them as little cores. Again I have no problems with what else you wrote here, it’s just not the right term to describe Intel.
I didn’t say there was anything “wrong” with Intel’s design. My point was that the reason that it exists is that Intel’s P-cores can’t compete against AMD P-cores in die area or power. It’s why Rocket Lake and Tiger Lake (Rocket Lake even worse I’ll admit) had difficulty scaling to larger core counts and competing in multithreaded throughput. Going heterogeneous is an ingenious solution to overcome that deficit - though it does come with drawbacks a few of which Intel will have to clean up with Raptor Lake.
Intel may get their ST performance crown but they use far more power to do it. Also it’s more like 6-16% for SpecInt/SpecFloat.
For MT performance, where Alder Lake really shines, yes DDR5 is absolutely necessary to get the full performance out of Alder Lake. In ST sure DDR4 can trade with DDR5, but it’s not even close on MT. Which makes sense as on a 12900K it’s trying to feed 24 threads from 16 cores. DDR4 simply doesn’t have the bandwidth. With DDR4, AMD 5950x matches (SpecFloat) or wallops (SpecInt) the Intel 12900K in multithreaded. With DDR5, that reverses. Intel wallops in SpecFloat and matches in SpecInt.
But that brings me to my last point - the most important point of this and the last post. Even with DDR5 and even with the midrange cores and even with Intel’s ST advantage, AMD still matches Intel in integer MT workloads. The reality is those midrange cores are more necessary for Intel than they are for AMD when it comes to multithreaded throughput. Raw ST performance is a non-sequitor since when it comes to MT, perf/watt is important and AMD still has an advantage here in the performance cores. Could similar midrange cores be helpful for AMD? Sure. Let’s see what Zen4 brings - to be clear AMD going heterogeneous is not going to happen this generation, but even seeing what AMD’s MT throughput is without midrange or true little cores will be helpful to determine when or if AMD might choose to use heterogeneous cores in their CPUs and what strategy they’ll employ. With the announcement of the Zen4 variants, some believe that represents the first step in AMD’s future heterogeneous cores (hence @leman’s link). Maybe.
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