Do you understand what you are talking about? Do you understand what those link mean, and what they are talking about?
Serious questions.
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M3 Chip Generation - Discussion Megathread
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Serious questions.
Yes, this would be most 3D user interfaces and 3D CAD and maybe apps like Blender. Really, any app except games. Even some kinds of games don't want to be photo-realistic.
If you do, then I will ask you this:
How is this picture, an SOC that is made from three separate dies fit into your picture?
Is it a GPU with integrated CPU?
How is Dragon Range APU:
Is it a GPU with integrated CPU?
How does all of it it fit into Unified Memory architecture?
Unified memory architecture, and General-Purpose Compute is all about homogenization of software, so that you can accelarate execution with the GPU, not the other way around.
Software has to always execute on the CPU and GPU, or any other accelerator has the capability of expanding its capabilities.
That was me, here, during the M1 Pro/Max event. It was off-the-cuff, and was in the context of people endlessly arguing about ill-defined terms, integrated vs “dedicated” GPUs (“discrete” is the proper terminology, btw) where the usual suspects’ toxic claims were that toy-like phone iGPUs couldn’t possibly perform well enough, etc., ad nauseam.
Well, it turned out that the M1 Pro/Max had an enormous amount of throughput and large caches; qualities of a well designed GPU (rather than a tacked on iGPU with anemic throughput). The fact is the ASi chips are SoCs with cores and other bits that are really capable, unique, well integrated with a healthy amount of secret sauce & magic, and overall pretty much amazing.
Sure, if you squint, it's a CPU with an iGPU, or a GPU with an iCPU, or whatever you all want to argue about. But, in the end it's still an SoC and all you all end up with is crows feet and frown lines.
Thank you for letting me know it was you. And thank you for providing the context surrounding your original statement. Now that you're here, in this lovely topic, please stick around if you would like to be argued to death.
As one of my favourite language philosophers once wrote "there is not much mystery in these things unless we go and make one out of it"
Saying something like 'wow, this SoC is more GPU as an GPU' (like @altaic did) is a great informal observation and a way to draw attention to some interesting features of the implementation. But attempting to make a technical discourse out of it (like @257Loner appears to do) very quickly derails into nonsense.
This is not about eroding the difference between CPUs and GPUs, but about making GPUs more useful outside of graphics domain. You are looking at the false dichotomy. This is not about "CPU" vs "GPU", this is about different class of problems. The GPU is a processor designed to solve massively parallel computational problems. And to achieves this capability you have to sacrifice something else. We have GPUs because the tasks they perform cannot be solved efficiently using the classical CPU approach. We have CPUs because the tasks they perform cannot be solved efficiently using a massively parallel processor. The magical word is "specialisation". Just like it's impossible to build a car that will excel both at top speed and cargo capacity, it's impossible to build a device that will excel both at serial and parallel computation. As long as we need both capabilities, we will have both types of devices, no matter how you call them or what shape they take (e.g. modern CPUs also have GPU-like parallel computation capabilities, just on a smaller scale, and an Apple GPU includes a custom ARM core to coordinate GPU work scheduling and execution ). And if anything, the industry goes more towards specialisation (so the opposite of what you are claiming). In addition to the serial specialists (CPUs) and parallel specialists (GPUs) we also now have convolution/matrix specialists (various NPUs/tensor units), compression specialists (video en/decoding, data compression hardware), image processing specialists, spatial data and audio specialists, the list goes on.
What purpose would this binary classification serve? There is more grey in the real world than just black and white. Anyhow, in my opinion they are neither. They are SoCs that contain CPU and GPU and a bunch of other things.
However if I do accept, for a moment, the premise of your question, I'd point out that the Mx Max still uses regular LPDDR5 memory while the Playstation 5 and Xbox Series X/S both use GDDR6 memory just like real GPUs do.
I speculate that the M3 is going to be faster than the M2 and M1.
I’ve been a long time observer of TOP, and my recent comments here are purely to help out. Maybe I’ll yammer you all soon.As one of my favourite language philosophers once wrote "there is not much mystery in these things unless we go and make one out of it"
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Technically Overboard with Peeps. The Other Persuasion. Choose your own adventure.
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Am I too old, too young, or maybe just too tired to get this?
Back on topic, I'm wondering whether the M3 generation will increase the size of the P-core clusters. The M1/2 Pro/Max/Ultra all group the P-cores into clusters of 4 that share an L2 cache. And each P-core can only access the L2 cache belonging to its cluster. Will Apple make a jump like AMD did when going from Zen 2's 4-core to Zen 3's 8-core clusters?
Does it need to be done in a linear fashion? Could it be a cluster of 5 or 6? I appreciate odd numbers result in n odd layout, but nothing a little Tetris can’t fix!
I don't think so, the extra memory bandwidth most likely will be used by GPU cores which I expect would be 1536 ALU.
Apple would increase CPU cores when LPDDR6 appears, earliest would be in 2026...
Either monolithic and 12 core GPU, with 4P/4E CPU, or tile based and 20 core GPU with 6P/6E CPU, with 192 bit bus.
The cluster size has nothing to do with (extra) memory bandwidth. It's about how many cores share an L2 cache, and how many cores enjoy the fastest core-to-core latency. Take the M1 Pro for example. The 8 P-cores are organised as two 4-core clusters, each with 12MB of L2. So while the combined L2 of the 8 P-cores is 24MB, each individual core can only make use of (at most) 12MB. As for the latencies: https://github.com/nviennot/core-to-core-latency
CPU still need to be feed with memory data, and they (CPU and GPU) all require enough memory bandwidth to support it. That's why M2 Pro needs 256-bit memory bus to support higher core count. GPU actually more sensitive to memory bandwidth cause they consists of small ALU to process. That's why it is combination of CPU and GPU needs for memory bandwidth. Of course power TDP and clock speed also have to count in here...
Yes, the CPU needs to be fed with memory data, but that has nothing to do with my question about whether 8 P-cores are organised as one 8x cluster, two 4x clusters, or whatever.