I have to quibble slightly with the terminology you're using here, only because using the correct words helps explain things a lot better.
What's visible in the picture is referred to as a "package" - not just a silicon chip (or chips plural) but an assembly of silicon into a package ready to be soldered to a PCB.
This style of package is a stackup which looks roughly like this in cross-section:
Code:
=========================== Metal Heatspreader
----------------- Apple Silicon SoC
* * * * * * * * * Microbumps
~~~~~~~~~~~~~~~~~~~~~~~~~~~ Organic Substrate
• • • • • • • • • • • • • • Solder Balls
"Microbumps" are tiny solder balls, much finer pitch than can be used to connect directly to a main PCB. "Organic substrate" is basically a very advanced PCB whose materials are carefully chosen to match the coefficient of thermal expansion of silicon and which supports ultra high ball grid array density (for the microbumps on one side) and very fine wiring pitch (because there's a lot more connections between silicon and organic substrate than substrate to main PCB).
Since Apple Silicon SoC packages also include DRAM, some parts of the package cross-section substitute an entire DRAM package with its own solder balls for everything above the organic substrate. This is called Package-on-Package because Apple's buying DRAM already in its own package and soldering it to their SoC package.
Calling this PoP is confusing.
PoP tends to refer to a very specific design of a DRAM package (not chip) mounted on a SoC package
This looks like one black "chip" stacked on another black "chip", like so:
the significant points include:
- vertical stacking
- the memory is connected to the bumps below the memory chip using thin gold wires. It's amazing that using these thin wires (many of them, all tiny!) is still the cheapest way to connect the DRAM chip to external bumps, but that's the way it is!
- if you look at the bumps of the DRAM chip, they tend to form a ring around the edge of the chip. Usually the SoC chip can then fit into the "blank hole" space in the middle of that ring, with the DRAM chip bumps connecting contacts around the SoC package, as shown in the image above.
Apple used to make A chips (ie for iPhone) this way, but for A16 (and from the very limited data I've seen, also for A17) this changed. A16 has a double-sided thin substrate (think something like a microscope slide but much thinner), with the actual SoC chip on one side, and the DRAM chip on the other side. The connection is now chip to chip, not package to package. There are no tiny wires connecting DRAM to bumps; instead there are tiny copper-filled holes (so-called TSV's) through the substrate connecting the DRAM contacts on one side with the SoC contacts on the other side.
This is thinner and lower power (less capacitance and resistance in the various parts of the connection of wires and bumps from DRAM to SoC).
This is described here (in Japanese)
https://eetimes.itmedia.co.jp/ee/articles/2210/25/news048.html and you can see it here when you know what you are looking at.
The upper section is molding (thick) then essentially the DRAM chips then DRAM bumps connecting to copper TSVs connecting to the SoC chip (the most complicated section) finally the bumps to the PCB. This is very low resolution so you see no details of the actual DRAM or SoC, you just see large thin copper power planes/redistribution layers.
It's unclear what the substrate is between the SoC and the DRAM, in part because of the Japanese translation.
The translation calls it glass, and that's certainly possible in theory; Intel is working on using glass for this sort of task.
Alternatively it could be silicon. Si is optimal for this because it has the same temperature expansion coefficient, so you don't get warping or cracking when the package heats or cools, the way you might if the substrate expands at a different rate from the SoC and DRAM.
Alternatively it could just be a fancy high quality (and very thin) "PCB board" so basically glass fiber embedded in epoxy resin, and that's how machine translation is picking up the word glass? All very unclear.
We won't do M series in this detail! But already you can see the point, that there are many different ways to do these things, and the differences matter in terms of z-height, area, power, etc.
For M series, instead of stacking DRAM above the SoC, either old PoP style or new A16/A17 style, we place the DRAM on the side. That involves a different set of technologies that move the power and signals "sideways" rather than vertically.
