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M4+ Chip Generation - Speculation Megathread [MERGED]
- Thread starter GoetzPhil
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Huh? Volume production began in Q4 2023: "N3E started volume production in the fourth quarter of last year, as planned, ..." TSMC executive commenting at their technology symposium in May 2024, widely reported, for example:
Hm, my mistake then. But it still seems fantastically unlikely.Huh? Volume production began in Q4 2023: "N3E started volume production in the fourth quarter of last year, as planned, ..." TSMC executive commenting at their technology symposium in May 2024, widely reported, for example:
If they really were in *volume* production that early, then they didn't need to stockpile for so long. And that ignores the whole issue of them voluntarily giving up months of dev time they could be using to progress their silicon further.
So OK, not impossible. I'd still bet heavily against it.
Quite plausible if it is cheaper to make than the "A18 Pro". If the 'new' cores (GPU and/or Display controllers in particular) soak up more die space than it is relatively likely that the A18 Pro die would cost more.
Yes, doing a re-spin of the A17 Pro would cost money. But the primary target for the A18 probably isn't the 'plain' iPhone 16. iPhone SE probably as at least as long a service life. possible AppleTV placement. possible entry iPad placement at some point. The 'problem' the A17 Pro has is that N3B is likely going to get turned off by TSMC once Intel 'quits'. That is pretty likely since Intel has double 'spun' the upcoming cores (at least for desktop Arrow Lake) on both Intel 20A and TSMC N3B. Long term Intel probably will internalize any die that makes it into a very long term product.
Once Apple replaces the "iPhone Pro" the A17 Pro is 'toast' in terms of volume. There is no 'hand me down' product. Apple does lots of 'hand me down' products with their SoCs. It is the modus operandi. So labeling that is "not plausible' is a stretch. If the production of the A17 Pro design completely dies in volume after a year what is the 'cost' of that? That too is pretty high ( an effective increase in amortization costs over potentially many millions of units being thrown away. )
The iPhone SE doesn't need bleeding edge A18 Pro performance. In fact, probably better for iPhone Pro sales if it doesn't have it. Apple TV doesn't really need it either. Entry iPad .. nope. Apple can probably slightly crank up the yields by binning down a GPU core ( e.g, A14X versus A14Z. )
TSMC N3E wafer costs are a bit lower than N3B wafers , but both are higher than N5-N4 wafer costs. And things aren't getting 'better' next year.
TSMC may increase wafer pricing by 10% for 2025: Report
Chips are getting more expensive.
where missing the boat is that a more expensive N3 or N2 generation dies are going to start to mismatch the 'entry' level iPhones and iPad on cost containment. ( there are also rumblings of new watch SoC. Similar issue N3E of A17 gen E cores is likely a better fit there. )
N3E backslides back to N5 SRAM/cache density. Trading off bigger die implementations for incrementally better defect yields. But bigger dies gets you less dies per wafer ( the die yield from wafer good or bad goes down. )
If there is no "A18 Pro" with a different die that would change things a bit. ( if the 'A18' and 'A18 Pro' are same die with some cores binned off. ). But if they are different sized dies then a re-spin of a foundation design that already works is likely cheaper. So it really isn't the 're-spin' cost that is the issue. If Apple is trying to save money by slapping different labels on the same A18 die then that would be the economic hurdle. If the A17-era die is 3-6% smaller that 'adds up' when doing 10's of millions of dies at substantively higher wafer costs.
Pragmatically, the A-series can be ruled out in the intermediate term. TSMC's advanced packaging technology has production limits. CoWoS is completely sold out for another year (and that is for ~1M/year run rates. Not 10's of millions). A-series would be using something inside of 1 reticle limits so probably volume scales better, but there is likely a volume cap. The other problem is that advanced packaging costs more money. non Pro -iPhones are sold for 3+ years. The price is going down each year as they age out.
The A-series dies are already relatively smaller ~90-100 mm^2 and the RAM is 3D stacked already. What exactly trying to stack? Relatively very small number of I/O ports (one). The modem and RF modules have their own power issues. (and Apple doesn't have a production modem yet anyway. And the interface between modem and compute die doesn't have to be some crazy high bandwidth rate either. 10Gb/s range; not 8,000Gb/s ) . They could possibly more the memory controllers and 'controller level cache off the main die but still likely would have some other smaller cache and still would have smaller i/o 'pads' to do die-to-die (that isn't 'free' space either), so die wouldn't shrink dramatically. )
Finally, the 3D packaging is a Perf/Watt hit. Even the advanced stuff. For 300-600 mm^2 dies there is a different tradeoff threshold than for 50-90 mm^2 ones. It is much easier to stay monolithic if already relatively small.
For small dies , flipping wafer over and doing 'back side' printing on the wafer is also going to hold off 3D bonding a bit longer than larger dies.
The iPhones have been on a 2D size creep toward bigger. So huge pressures to come up with a smaller SoC package size really isn't there.
You are presuming that they didn't already have an A17 on N3E as a 'Plan B' when N3A turned into N3B . The number of SoC design companies balking at the initial, expensive version of N3 was pretty high early in the process. (even without supposed 'yield problems' N3A/B was going to be both expensive and an inventory headache due to longer 'bake' times. ) Apple should not have been surprised that practically no one else showed up on N3B (and Intel being the only other high volume one was a dual edged sword. They were not likely to keep a predictable schedule of on time delivery. )
AMD has Zen 5 on both N4 and N3E. They did them in a overlapping pipeline fashion. If you have the people to run another development pipeline then there isn't 'extra months'. It is just months into another design allocation pipeline. Apple has folks working on R1. Watch SoC. etc. Everything isn't all A-series all the time.
Apple could have wrapped up the N3E port not that relatively long after they mostly wrapped up the N3 A17 Pro and several months before N3E went into volume production. N3E is a different design library but it is also 'eases' constraints ( less aggressive). Some 'problems' should have gotten some relief (by offsetting on using up more space).
That the M4 (on N3E) arrived before the A18 is not much of an indication of some onerous delay at all. These are not being finished 'just in time'. N3B missing the iPhone production window in 2023 should have been obvious years ahead of time. The notion of some hectic scramble to N3E seems to be more unlikely.
You're a bit difficult to read, as usual, but those are some quite interesting ideas.
In essence, I think, you're saying that there is room in Apple's product line for a mid-core. Not an E core, but not quite the current P core either. That's obviously true, in that they had exactly that in previous years by using year-old chip models. And since the pending demise of N3B means they can't pursue that usual strategy this year, they will build a new mid-core on the current leading-edge process instead.
So OK, I withdraw my previous statement. You have indeed identified a plausible scenario where they'd reimplement A17 cores on N3E. I still think it's unlikely. Much more likely they will do two chips with the same core designs, but different numbers. (Perhaps the Pro will have 2P+6E, or as has happened before, more GPU- though AFAIK previous differences were all fused-off cores, not different designs.)
Apple has been well-served by putting more CPU silicon into their products than they have to. And they're taking real heat right now for failing to do so in another arena (RAM, due to AI). I strongly doubt they're going to change that now.
Unrelatedly, I completely agree with your other post: there is no reason for Apple to use advanced packaging for A chips in the next few years. Monolithic at that size is a no-brainer. The one exception to that is if they finally get their 5G chip ready for prime time, it will likely be done on another process, and I can see them doing some sort of fancy packaging to connect it to the main chip. Not because of speed/bandwidth, as you pointed out, but for energy efficiency. Though even there I'm not sure there's enough savings to be had to make that worthwhile.
How could N3E be "plan B"? N3E was never going to come before N3B. Plan B would have to have been N4something, using previous-year's cores. Likely, exactly the kind of thing we got with the M2.
Obviously Apple has multiple design teams. I know (annoyingly tight-lipped) people on two of them. I don't think that matters here.
(Also you mean "production window in 2022", not 2023. They hit 2023.)
Advanced packaging will help:
+) HPC - where lower latencies from shorter signal paths will allow greater CPU/NPU/GPU linear performance scaling.
+) Apple Watch - where minimising power lost through disparate signaling will translate into longer battery life, and SoC footprint reductions will allow for thinner (and lighter) devices.
+) Data Centre server chips (2026) : Where 9 x Reticle limit ‘SoC beasts’ could leverage stacked tiles where thermal considerations permit.
If it transpires an overriding reason the iPad was given an M4 ‘early’ was to address issues of fanless heat dissipation when doing (future) AI workloads with limited surface area (that might also be in sunshine) - perhaps advanced packaging for the iPhone will become a necessity for Apple to differentiate its offering in the same thermal envelope as its competition (especially with its even more limited surface area)
+) HPC - where lower latencies from shorter signal paths will allow greater CPU/NPU/GPU linear performance scaling.
+) Apple Watch - where minimising power lost through disparate signaling will translate into longer battery life, and SoC footprint reductions will allow for thinner (and lighter) devices.
+) Data Centre server chips (2026) : Where 9 x Reticle limit ‘SoC beasts’ could leverage stacked tiles where thermal considerations permit.
If it transpires an overriding reason the iPad was given an M4 ‘early’ was to address issues of fanless heat dissipation when doing (future) AI workloads with limited surface area (that might also be in sunshine) - perhaps advanced packaging for the iPhone will become a necessity for Apple to differentiate its offering in the same thermal envelope as its competition (especially with its even more limited surface area)
I think @deconstruct60 means N3E was a Plan B to begin with. When they say “when N3A turned into N3B” they mean when TSMC shifted to N3E (and N3 became N3B).
I mean, there was a time when Plan A was in place, with N3 and N3P on the roadmap. That changed when N3E replaced N3 on the roadmap. Let’s not forget this move was completely unprecedented. This wasn’t standard operating procedure. Moreover, it’s not far-fetched to assume Apple was intimately involved in the decision to switch to Plan B (N3E), so really the more we talk about this, the more plausible this A18 = A17 Pro + N3E rumor sounds, to me, at least.
That's what doesn't make any sense though. As @Confused-User was saying manufacturing A17 Pro on N3E can't have been a Plan B to making the A17 pro on N3/N3B because N3E could never have been ready on time. Apple was never going to delay the iPhone, so Plan B was either prepping A17Pro on N4 of some variety or not releasing an A17 Pro.
N3B replaced N3 (and really was just a rebadge).
I disagree
.Yeah if A18Pro is significantly bigger than A17Pro because it uses a bigger design then the cheapest option is not to port A17Pro to N3E and produce that as well but to bin the A18Pro. You recover more of your A18Pro dies and you don't have to incur the costs of porting. Heck and if you are going to the bother of producing two A-series dies on the same node, why would you port the core over when you already have the more advanced core designed and ready to go? It'd be just as easy to design a smaller SOC at that point with the A18 core than redo the physical design of the entire A17 Pro on N3E.
I mean @Confused-User and I could indeed be wrong. It's just none of the explanations put forwards really make any sense.
I don’t think anyone is saying that, hence the confusion, at least I’m not saying that. This wouldn’t be a Plan B for “making the A17 Pro on N3/N3B” — it would be a Plan B for making the A18/M4 on N3P. Plan A was abandoned when N3E displaced N3/N3B as the basis for N3P, pushing N3P back a year or so.
To be clear, I’m not invested in arguing for or against the veracity of the report, I’m just interested in understanding how it could be, if indeed it is true.
Well, I’m stuck in an airport, 20 hours into what was supposed to be a nice 3-hour direct flight. So plenty of time to ponder the universe…
This part is not very convincing to me.
I don't think the CPU core area covers enough of the chip to make binning a viable path forwards. That is, you won't recover enough chips that are usable with one fewer CPU core working that you can supply all (or even much) of your needs for an A18 non-Pro.
It's also not clear to me what tier you'd establish for a non-Pro chip. 2P+4E seems like a minimum viable A18 these days. So what does the Pro look like? 3P (much less 4P) seems unlikely, you're verging on M4 territory. 6E seems possible, but the amount of space going to those two extra E cores isn't much, so the chances that a defect will be found within them is very small, again making binning not a viable strategy for recovering lost silicon (of course it's totally viable for market segmentation).
It's maybe a bit more plausible that the Pro would have more GPU cores than the non-Pro. Those are larger, making the viability of binning a bit better. Still not great though. There's also precedent for this, Apple having done it before.
I think if Apple wants to pay less for silicon, it'll make two mask sets, one for A18 and one for A18Pro. Will the savings be worth it? ...maybe. I think only they really know enough to even have a good opinion.
Indeed binning GPU cores would make more sense as the main part of the bin, because yeah binning two E cores off of a possible 2+6 design which is the most you can do doesn't sound great ... but because then 2 E-cores doesn't add much silicon die area so saying that A18Pro would be more expensive to make on the basis of adding more cpu cores also just doesn't work. So porting A17Pro would still be an odd decision.
Yeah.
Oh okay, I think I understand, but I don't think that works either though. It's not clear that N3P was significantly delayed relative to everything else so it's not clear why they would've planned to use it for A18/M4 - it's possible they might use it for the Brava/Hidra dies, maybe, since those won't be out until November and be much lower volume, but we don't know that yet. And it's not clear why A17Pro on N3E would be the primary backup plan as opposed to making the A18/M4 on N3E which is what we know actually happened - at least for the M4. So that would make the A17Pro on N3E be a Plan C in that scenario and since plan B in this universe would appear to be in action, we have the M4 on N3E, why would they also pull the trigger on Plan C? This is of course presupposing that A18/M4 on N3E wasn't always Plan A, which we don't know that it wasn't.
Of course it'll be hilarious if there isn't an A18Pro at all. It's all just A18 (I know all the rumors point to a Pro/base split, but still they are just rumors). And as @Confused-User said, we really don't know what the A18Pro is supposed to look like. Like will it even have a different CPU cluster layout? Maybe? More GPU cores sounds plausible.
Absolutely. I just can't wrap my head around why this would be the case, but maybe that's "a me problem".
Have a good flight.
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Eliyan presentation from March (the relative bit) pitching the approach for their UMI standard:
Most likely it seems M5 will be the redesign of the physical hardware, coming with OLED panels right? I'm personally not planning to move from the M2 Pro unless they add some new display panel and make it slightly slimmer at least for the 14".
I think the M5 will be the biggest upgrade since M1, and that's saying a lot since M4 looks to be a solid upgrade as well, and M3 was not shabby either.
My hopes are for great GPU improvements, CPU I don't care about anymore since it demolishes already, and efficiency improvements meaning better thermals and battery life. Think if they could manage RTX 4070 performance in the M5 base package, that would be phenomenal.
Apples ability to create a 'super powerful' system may be limited the maximum heat dissipation of the device in question.
If the Mac Studio M2 Ultra maxed out at 295 Watts - and a new M chip is can reach 1.5 x times that system performance in the same thermal envelope - then that is what the software writers have to work with.
N3P will 'allow' Apply to get 10% more power in the same thermal envelope.
If Apple are able dissipate 21% more heat than the current Studio design.
1.5 x 1.1 x 1 (current 295 watt dissipation) = 1.65 x times faster than the M2 Ultra
1.5 x 1.10 x 1.21 (21% more = 357w) = 2 x times faster on paper than the M2 Ultra
www.anandtech.com
If TSMC's N2 provides an 18% improvement in performance per watt over N3P, and Apples GPU/NPU performance per watt is already leading in the consumer space - those wanting to invest a small fortune into an Apple HPC with the physical volume of the Mac Studio should take comfort knowing this machine hardware will remain relevant for many years to come.
TSMC A16 will be up to 32% faster than N2 = 1.56 x faster then N3P - with the earliest Apple Mac out in 2028.
That would mean waiting 3 years for a new Studio to go 30% faster - or waiting for the machine after that (5 years+) for a machine has could have (speculation) 50% more hardware performance.
Perhaps what people really need is optimised frameworks to be available - and mature tools from Apple for developers to understand how get (often multi platform) their code base working efficiently with the minimum design changes and forks in their code.
AI frameworks are going to get the most dramatic performance gains from redesigns of frameworks that work on two year old hardware - rather than hardware that came in the last quarter.
Perhaps what we want is Apples Lowest performance devices have a hefty excess of computation power - so that software writers tune the offerings on already capable machines? Something that will lead to far more sales and less FOMO.
If the Mac Studio M2 Ultra maxed out at 295 Watts - and a new M chip is can reach 1.5 x times that system performance in the same thermal envelope - then that is what the software writers have to work with.
N3P will 'allow' Apply to get 10% more power in the same thermal envelope.
If Apple are able dissipate 21% more heat than the current Studio design.
1.5 x 1.1 x 1 (current 295 watt dissipation) = 1.65 x times faster than the M2 Ultra
1.5 x 1.10 x 1.21 (21% more = 357w) = 2 x times faster on paper than the M2 Ultra
TSMC's Roadmap at a Glance: N3X, N2P, A16 Coming in 2025/2026
If TSMC's N2 provides an 18% improvement in performance per watt over N3P, and Apples GPU/NPU performance per watt is already leading in the consumer space - those wanting to invest a small fortune into an Apple HPC with the physical volume of the Mac Studio should take comfort knowing this machine hardware will remain relevant for many years to come.
TSMC A16 will be up to 32% faster than N2 = 1.56 x faster then N3P - with the earliest Apple Mac out in 2028.
That would mean waiting 3 years for a new Studio to go 30% faster - or waiting for the machine after that (5 years+) for a machine has could have (speculation) 50% more hardware performance.
Perhaps what people really need is optimised frameworks to be available - and mature tools from Apple for developers to understand how get (often multi platform) their code base working efficiently with the minimum design changes and forks in their code.
AI frameworks are going to get the most dramatic performance gains from redesigns of frameworks that work on two year old hardware - rather than hardware that came in the last quarter.
Perhaps what we want is Apples Lowest performance devices have a hefty excess of computation power - so that software writers tune the offerings on already capable machines? Something that will lead to far more sales and less FOMO.
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I'd be happy with more Battery Life when compared to M1/M2 Pro and a more smallish design for the 14" Pro.
Apple's hardware is using considerably lower TDPs than other chips of comparable size. For example, Intel's enthusiast-class CPUs have die size comparable to the Mx Pro chips, yet can consume an order of magnitude more power. Heat dissipation does not seem to be a limiting factor for them. I would say the biggest performance limiter is their desire to build systems that perform well on thermally constrained targets, which requires certain architectural and engineering choices.
It sounds a bit over the top. Are you saying that Intel's CPU consumes 10 times more than Apple's SOC?
It's more like 4-5x, but his point still stands.
RTX 4070 in the *base* M5??? That seems hopelessly optimistic to me (and I'm pretty optimistic when it comes to AS).
I was thinking, what qualifies as an "order of magnitude" exactly? If you think about it as a statement about log10() - and I don't think anything else makes sense - then anything from 5x to 50x is going to be one order of magnitude, 50x-500x is two orders, etc. So given that, the statement... may be true, depeneding on exactly what you're measuring, but it's not a slam dunk.
Either way though, I agree, leman's larger point stands.