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M4+ Chip Generation - Speculation Megathread [MERGED]
- Thread starter GoetzPhil
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We went M1 -> M3 with no TB4 support so Apple could easily drag out TB5 implementation on M5.
Yeah while I think it’s funny my 1 min calculations turned out pretty much correct, I am merely pointing out how easy it is to make ”educated assumptions” by just using putting one and one together. And since that is the case, I dont see the point of these ”leakers” status at all. They should be fired and do something worthwhile instead.
Yes, but we already have TB5 into the M4pro/Max
Maybe besides M5, TB5 could be a good addition for the ipad pro users along side with the "so called" Studio Display
and support for native DisplayPort 2.1 output over USB‑C
And M1 Pro/Max to M3 Pro/Max all had TB4 yet Apple was fine keeping TB3 on the base models (and single external display support). Maybe they’ll have a change of heart and move to TB5 earlier on the base models but I’m not hopeful based on their previous behaviour.
It indeed would be nice.
I think that since the TB5 standard is inflexible in its mandatory 80 Gbps bi-directional bandwidth as standard, supporting two minimum and three optional monitors per channel, I think that the chance of Apple incorporating all that graphics power in its base M5 chip is minimal.
At best the base will most likely get one monitor per channel and USB4 V2 80Gbps data bandwidth.
Just because the silicon is on the SoC for everything except more monitor support.
And only the Pro and higher will be SoIC.
At best the base will most likely get one monitor per channel and USB4 V2 80Gbps data bandwidth.
Just because the silicon is on the SoC for everything except more monitor support.
And only the Pro and higher will be SoIC.
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ST 4600 MT 24000 GPU 94000
6P + 6E + 12GPU
See, that's easy.
Now to stay a prophet after the first test, that's the difficult part. 😉
SoIC is going to make the GPU inherently better how? For RDNA 4 AMD dropped the chiplet approach they dropped chiplets for their dGPU offerings.
For the APU ( "Halo") class the CPU cores were already in a chiplet in the first place. The "everything else" is basically monolithic once exclude covering the CPU cores.
Apple going down the path where the CPU cores are pushed off into an exclusive island doesn't really buy much for them. The Pro , Max are very highly skewed toward being the GPU ( GPU cores + Display Engines+ media coprocessors ) anyway in the first place.
That’s not what I meant to say. I mean, if they are using SoIC for Pro/Max/Ultra, then it must be to gain some kind of advantage. We can assume Apple’s priorities haven’t changed. So what does SoIC allow them to do better?
These are not mutually exclusive:
1) Wafer flexibility: e.g. a) potentially stacking cache made on cheaper nodes onto logic made from more expensive nodes, possibly allowing for even more cache (especially SLC - think AMD 3D-cache) for cheaper; b) using cheaper wafers for I/O vs logic, wouldn't necessarily be 3D stacked but still using the SoIC platform
(Edit the below points would be using the non-3D stacking, 2.5D interposer for SoIC)
2) Die reuse: if part of the die is going to be the same across all the variants, it could make sense to separate it out and attach the other pieces to it
3) Die flexibility: this almost a 2a) but you could imagine that say Apple wanted to build a GPU-heavy SOC variant, you would attach a CPU die to two GPU dies. A variation of this idea with even more flexility would be personally the most exciting but I wouldn't necessarily get my hopes up that Apple's first iteration of chiplets/tiles for the Pro/Max will allow for this as Apple may be more conservative, testing it out first but building otherwise familiar Pro/Max chips (in fact what I've described here would be just a formalization of the current M4 Pro/Max design).
So number 1) could lead to performance improvements if it allows for extra cache (it could also allow for cheaper cache) and number 3) could lead to performance improvements in a sense because the user could better tailor exactly what kind of performance they want to spend their money on - CPU-focused or GPU-focused or both. But again, the combinatorics of that could be technically/logistically challenging - Apple could technically already offer binned Pro-like CPUs and full Max GPU SOC combinations and ... don't (or full Max CPU and Pro GPU for that matter, though they did with the M2). SoIC might not change that.
Yup, basically my points 2 and 3 are this. AMD has also done basically done all of these at some point.
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There are a couple of recent articles at SE on stacking. In first forays... "an easier first step" (used by Qualcomm) for "20% to 30% improved power efficiency" is mentioned. Something else Apple might be inclined towards...
https://semiengineering.com/first-forays-into-true-3d-ic-designs/
https://semiengineering.com/how-to-cool-3d-ics/
... +SLC if the M5 leak is an indicator.
Apple's priorities so far has been
1. Perf/Watt.
2. Fewer/Narrower package solutions delivered over wider set of products. (economies of scale in volume and length of individual package design usage/deployment ). Also ease to product at volume matters.
Tightly coupled to that at the product line up level : don't make everything for everybody. Even the list of products being distributed to is not very large.
3. Relatively narrow range binning for segmentation for a specific package/die. 1-2 CPU cores binned out. Or 2-4 GPU cores binned out.
Product segmentation also restricts and confines I/O. ( so not uniform across in a product line up. )
So in turn...
Perf/Watt : Versus monolithic SOIC raises or lowers Perf/Watt. SOIC is lower power than previous die packaging interconnect, but have the previous ones been better than monolithic?
Could SOIC help delivery a next gen "UltraFusion 2" that had better Pref/Watt characteristics? Yes. But that wasn't monolithic in the first place.
Two ( c and d) out of the three examples TSMC list for SOIC on this diagram are for horizontal (more a interposer connect than stacking of denser logic) at least as much as vertical moves.
TSMC-SoIC® - Taiwan Semiconductor Manufacturing Company Limited
B is somewhat over representative because probably cannot cover 'logic' lower layer chip relatively hot spots with a cache chip (e.g., AMD "3D V-Cache" ).
Package reuse :
M1 in iPad Pro ( then iPad Air) , MBA , Mini , and iMac.
As go bigger die the product spread gets narrower.
die reuse M2 Max M2 Ultra.
Something like AMD's 3D V-cache augments a line up of 5 Ryzen products by another 3. Apple only has M1 , Pro, Max and sometimes Ultra. Apple has less base offerings before even adding the V-Cache options. Mix in AMD Epyc and even wider SpC product line up that is being covered. Is Apple out to sell every SoC perumation possible? Probably not.
A failed V-Cache bonding and if can fuse off the layered cache part , then still have a working product. If all (or vast majority ) of cache was in broken connection then not so much. The stacked die could be cheaper (old fab process and/or just much smaller) , but it isn't from defects either ( sometimes going to loose two or more good dies).
The other question would be what is the run rate TSMC can do with SOIC.
It also costs money to do.
"...
- SoIC-P is based on 18-25μm pitch μbump stacking and is targeted for more cost-sensitive applications, like mobile, IoT, client, etc.
TSMC 2023 North America Technology Symposium Overview Part 3 - Semiwiki
TSMC's 3DFabric initiative was a big focus at the symposium, as it should be. I remember when TSMC first went public with CoWos the semiconductor ecosystem, including yours truly, let out a collective sigh wondering why TSMC is venturing into the comparatively low margin world of packaging. Now...
semiwiki.com
If 'dirt cheap' then wouldn't need a more affordable option. if already have a managable size die ( sub 200mm^2) then is 5-8% bigger on N2 more expensive than the overhead costs of 'gluing' that extra 8% on afterwards?
Also back to tsmc SOIC page.
SoIC isn't making InFO_PoP necesarily disappear in most applications. ( pretty good chance that POP is cheaper in many of those DRAM to SoC connection contexts. Although it could help thermals to take the DRAM off the top and put it to the size of a smaller 2-D footprint chip. ( doesn't help M-series much though because not stacking DRAM to screw up thermals in the first place. )
Relatively narrow range of binning :
Apple charges a hefty premium for most "built to order" options. At the core they don't like complicated and/or expensive inventory. ( i.e., not out to sell everything to everybody). N2 wafers costing more , 16A costing thousands more , 14A costing thousands more will push Apple into SoIC to control costs. But as long as Apple can manage to pass along increase base costs into the product, they'd probably stick with the simpler inventory 2D/monolithic approach. ( e.g, Apple isn't covering Ultra at every iteration. Highest end stuff churns slower in Mac market. )
The broader context of that Qualcomm solution quote.
" ... which is that instead of stacking memories or logic, you solve the power delivery problem. The Qualcomm Nuvia chip has 3D capacitors embedded in the package. That brings 20% to 30% improved power efficiency. Technically, it’s 3D, but at a lower risk problem statement. ..."
Instead of stacking memories or logic is extremely indicative that are talking about something other than SoIC. Stackin logic pretty much is SoIC.
https://semiengineering.com/how-to-cool-3d-ics/
Which ends ...
" ...
Mueth: Standard packaging is for standard applications. But we’re not talking about standard applications here.
Posner: I personally do not see 3D going mainstream for many years because of the risk, the complexity, and the cost. What you want to do is create tools that solve very specific, big customer use cases on an application-by-application basis.
..."
Not sure how "not mainstream" aligns with higher volume Apple SoC packages. The higher the package volume deployment the more 'mainstream' it would be.
They have different classes of products, with different tradeoffs. For example, very low baseline power consumption is essential to Ax and Mx series, but less so for Mx Max.
Looking at the wording from Apple patents describing stacked die solutions, a focus appears to be on increasing the effective transistor budget without increasing the package area. This is why they empathize 2.5D stacking instead of flat tiles. I think @crazy dave is spot on here — if I can move secondary blocks like SLC, memory caches, display controller, etc. to a secondary die (maybe using 5nm process), then I have more effective area for compute. This approach will certainly use more power than a monolithic die on a cutting-edge process, but it might be worth it for prosumer chips.
Isn't B flipped with the most recent V-Cache design, eliminating the logic die hotspot concern? I don't see why Apple couldn't do the same.Apple's priorities so far has been
1. Perf/Watt.
2. Fewer/Narrower package solutions delivered over wider set of products. (economies of scale in volume and length of individual package design usage/deployment ). Also ease to product at volume matters.
Tightly coupled to that at the product line up level : don't make everything for everybody. Even the list of products being distributed to is not very large.
3. Relatively narrow range binning for segmentation for a specific package/die. 1-2 CPU cores binned out. Or 2-4 GPU cores binned out.
Product segmentation also restricts and confines I/O. ( so not uniform across in a product line up. )
So in turn...
Perf/Watt : Versus monolithic SOIC raises or lowers Perf/Watt. SOIC is lower power than previous die packaging interconnect, but have the previous ones been better than monolithic?
Could SOIC help delivery a next gen "UltraFusion 2" that had better Pref/Watt characteristics? Yes. But that wasn't monolithic in the first place.
Two ( c and d) out of the three examples TSMC list for SOIC on this diagram are for horizontal (more a interposer connect than stacking of denser logic) at least as much as vertical moves.
View attachment 2562591
TSMC-SoIC® - Taiwan Semiconductor Manufacturing Company Limited
3dfabric.tsmc.com
B is somewhat over representative because probably cannot cover 'logic' lower layer chip relatively hot spots with a cache chip (e.g., AMD "3D V-Cache" ).
Package reuse :
M1 in iPad Pro ( then iPad Air) , MBA , Mini , and iMac.
As go bigger die the product spread gets narrower.
die reuse M2 Max M2 Ultra.
Something like AMD's 3D V-cache augments a line up of 5 Ryzen products by another 3. Apple only has M1 , Pro, Max and sometimes Ultra. Apple has less base offerings before even adding the V-Cache options. Mix in AMD Epyc and even wider SpC product line up that is being covered. Is Apple out to sell every SoC perumation possible? Probably not.
A failed V-Cache bonding and if can fuse off the layered cache part , then still have a working product. If all (or vast majority ) of cache was in broken connection then not so much. The stacked die could be cheaper (old fab process and/or just much smaller) , but it isn't from defects either ( sometimes going to loose two or more good dies).
The other question would be what is the run rate TSMC can do with SOIC.
It also costs money to do.
"...
..."
- SoIC-P is based on 18-25μm pitch μbump stacking and is targeted for more cost-sensitive applications, like mobile, IoT, client, etc.
TSMC 2023 North America Technology Symposium Overview Part 3 - Semiwiki
TSMC's 3DFabric initiative was a big focus at the symposium, as it should be. I remember when TSMC first went public with CoWos the semiconductor ecosystem, including yours truly, let out a collective sigh wondering why TSMC is venturing into the comparatively low margin world of packaging. Now...
If 'dirt cheap' then wouldn't need a more affordable option. if already have a managable size die ( sub 200mm^2) then is 5-8% bigger on N2 more expensive than the overhead costs of 'gluing' that extra 8% on afterwards?
Also back to tsmc SOIC page.
View attachment 2562592
SoIC isn't making InFO_PoP necesarily disappear in most applications. ( pretty good chance that POP is cheaper in many of those DRAM to SoC connection contexts. Although it could help thermals to take the DRAM off the top and put it to the size of a smaller 2-D footprint chip. ( doesn't help M-series much though because not stacking DRAM to screw up thermals in the first place. )
Relatively narrow range of binning :
Apple charges a hefty premium for most "built to order" options. At the core they don't like complicated and/or expensive inventory. ( i.e., not out to sell everything to everybody). N2 wafers costing more , 16A costing thousands more , 14A costing thousands more will push Apple into SoIC to control costs. But as long as Apple can manage to pass along increase base costs into the product, they'd probably stick with the simpler inventory 2D/monolithic approach. ( e.g, Apple isn't covering Ultra at every iteration. Highest end stuff churns slower in Mac market. )
It wasn't eliminated. AMD worked out some bugs of layering SRAM on SRAM that required the to down clock the whole chip at bit. They still are not covering the more substantive hot spots (e.g. cores or very long distant signal drivers ) on the chip with SRAM.
The MI300 series there is some cache on the bottom but not on the top and those packages are thermal problem children compared to what interiors to Apple products.
AMD has a deeper need for CPU V-cache because they pulled the CPU cores away from memory and have uniformly slower access to minimize the NUMA issue. Apple's designs have always been cache 'heavy'. Pouring more ketchup on top of already large dose of ketchup probably won't see the same kind of improvements that AMD gets.
AMD also roughly collects all the bottom level SRAM into one place on the lower die. (created one big landing target for the V-cache). Apple's basic set up doesn't really do that. SLC cache is being shared by several different types of cores and is used to 'front' the memory system (which is relatively large (compared to AMD) and distributed around the die. )
If take the fab density gains to make the cores/logic smaller then in a zero sum die size puzzle they can add more area budget to the cache ( grow them larger in the monolthic die). N3P is also suppose to incrementally improve SRAM (not quite to N3B levels , but better than the N5 stuff. )
the Max's construints certainly bleed into the Mac Pro constraints. Apple's notion that these packages are perfectly optimized to for each product is a bit overblown.
Pushing the Max power consumption higher will backslide the mBP 14" ( and lessor extent the 16"). Perhaps will get some power savings elsewhere ( screen) to offset.
His proposed variant of mix-and-match CPU/GPU tiles are not going to vertically stack well. So that isn't spot on.
Additionally Apple wanting to keep the package size the same and "do more" inside the package is also aligned with not wanting more SoC skus/variants.
If Apple wanted to pack more into a Ultra (two Max die) set up then, yes what you outlined would be what they would be pulled into. But this is still largely just clinging to the very chunky, really non-chiplet approach to construction. Pretty good chance it would be herded into just the Max just like UltraFusion was.
Very top of the "prosumer" market means Apple would probably treat it as being more price elastic and being more expensive would just get passed along to endusers (e.g., Mac Pro base price going up 100% in 2019). That isn't exactly along with most of the normal product line strategy.
The Pro being stuff into the super shrunk Mini chassis means it isn't particular free to backslide on that front even though a "desktop". If the Max is causing the battery life on MBP to backslide then doing the same to the Pro doesn't really help that product subsegment.
P.S. the die size bloat creep on the Max has been real
M1 Max 432 mm^2 ( 2x this was creeping close to being a reticle limit bust )
M2 Max 510 mm^2.
M3 Max 600+ mm^2
M4 Max ?? ( even if came backwards a bit ... it is still quite large after the M3 "pork out")
When High NA EUV phases in eventually, this would largely be the same problem as what drove UltraFusion in first place ( 429 mm^2 reticle. down from 858mm^2 )
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Ah I see your confusion. I wasn't suggesting that the logic dies would be vertically stacked - SoIC allows for both vertical and 2.5D interposer connects (as Apple already uses for its fusion connector). That would be option c) in your figure above. I admit I didn't explicitly mention that for logic in parts 2/3, but I assumed that was obvious and I did say it when discussing moving things like I/O to a different die (which I said would not be necessarily by vertically stacked, that should have been a stronger negative). I will edit it that to make it more clear. Vertical stacking, if it is coming at all, is likely restricted to cache (and maybe capacitors as mentioned in the interviews provided by @treehuggerpro - also as stated in his links, 3D stacking of logic, is likely to remain exotic for quite some time).
My post is more theoretical about what Apple *could* use SoIC-mh for in the Pro and Max line as Kuo and Ma have both released notes suggesting that will be implemented - Kuo specifically in the M5 Pro/Max. If my memory is right he specifically mentioned the 2.5D connector, not 3D. If so, vertical cache is less likely for the M5 Pro/Max. Ma's note on the subject was from awhile ago and if memory serves merely mentioned that Apple would explore using tile-like structures for its Pro/Max line of chips for the M5/M6. This could be wrong of course.
So if it's coming, splitting some fraction of the die onto a cheaper wafer, including cache, and/or mix and match CPU/GPU tiles could be the approach Apple takes, though again I agree with one of your earlier posts that even in the latter case Apple may not expand the variety of their offerings as much as the approach would technically allow.
Yes
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This rumor appears to be based on a single source, a blog post here:
https://heyupnow.com/blogs/feature-...d-process-for-peak-performance-and-efficiency
If true, sounds expensive. I couldn’t find anyone else repeating the claim, other than clueless AI.
Here are the announced Qualcomm specs:
https://www.qualcomm.com/content/da...cuments/Snapdragon-X2-Elite-Product-Brief.pdf
Secure your app with Memory Integrity Enforcement - Meet With Apple - Videos - Apple Developer
Discover Memory Integrity Enforcement (MIE), a new security technology where hardware, the operating system, and the compiler work...
Historically the. nX variant from TMSC soaked increased power leaked to snag speed gains. For a mobile chip that doesn't particular make sense to toss perf/watt to hit is single thread drag racing benchmark.
N3X has more permutations.
N3 tab at this site.
"... TSMC’s N3X technology was introduced in 2023. We have validated the speed benefits and minor leakage trade-offs in silicon. N3X is 5% faster under the same area using a 2-fin standard cell than N3P. If a design currently uses TSMC’s 3-2 fin FinFlex standard cell to meet speed targets, customers can leverage N3X to achieve the same speed and reduce area by 9% by using 2-fin standard cells instead. N3X also improves power efficiency by lowering the supply voltage. ..."
Sound a bit like 'have cake and eat it too'. , but cannot do all of that at the same time.
Chart here has the results laid out a different way.
"..
| N3 vs N5 | N3E vs N5 | N3P vs N3E | N3X vs N3P | |
| Power | -25% ~ -30% | -34% | -5% ~ -10% | -7%*** |
| Performance | 10% - 15% | 18% | 5% | 5%, Fmax @1.2V** |
| Density* | ? | 1.3x | 1.04x | 1.10x*** |
| HVM | Q4 2022 | Q4 2023 | H2 2024 | H2 2025 |
**At the same area.
***At the same speed.
..."
TSMC's 3nm update: N3P in production, N3X on track
The last and final FinFET node from TSMC lives on.
Also N3X doesn't make much sense since production didn't start until H2 2025. If they had originally wanted to ship finished product in H2 2025 that is too late. ( your finished N3P designs could be sitting on the shelf for more than several months because the N3X stuff can't ship).
In post 2013 there is link to Qualcomm docs.
"...
X2 Elite Extreme. X2E-96-100 max clock 5GHz 288 GB/s
X2 Elite X2E-88-100. max cloc 4.7GHz. ( 5GHz is 6% ) 154 GB/s
X2 Elite X2E-80-100. max clock 4.7GHz. ( 5GHz is 6% ) 154 GB/s
..."
The gap is more likely driven by a combination of binning ( the 96 and 88 very likely share a common die) and memory bandwidth ( Extreme has better bandwidth so don't 'starve' the cores more easily. ) The RAM is packaged more energy efficiently also (on package). [ The other two have more modular RAM bit that comes with a trade off. ]
It makes about zero economic sense to fab the 98 and 88 on different die masks and fab process ( even if base design rule compatible). All they have to do is "bin down" a N3P they already have for the Extreme. Costs about $0.0 in additional R&D overhead. ( And gives Qualcomm substantively more resource to work on a phone version. )
The 80 is likely a different die. ( I/O provisioning different ( 12 PCI-e v5 versus 8 v5 for the '80') , GPU different , Display out support different , etc. ), Not running the clocks at the max extremely range gets them better effective yields. Since this is likely the higher volume SKU that makes gobs of sense.
As for Apple, it seems somewhat often folks throw "nX" process node at the largest M-series option because they have their underwear in a twist that the plain M single threaded performance is about the same as the Max/Ultra package. If paying several hundreds more for a package that the single thread drag racing potential so go sky high.
If Apple was dramatically loosing the single threaded race then that make some sense as a trade off , but they are not. What Apple has is a die that has to cover a very broad set of functionality implementations. SSD controller needs N3X for what reason? TBv5 ? Security Enclave? Audio decoder fixed function logic ? Tossing Fin-Flex out the window may not buy an overall die density improvement. (depends upon on just how heavily Fin-Flex is used in the baseline design. TMSC's numbers are based on some Arm design for a generic die. ( It isn't the same logic mix that Apple does. )
Apple's Max doesn't have quite the "almost reticle busting" problem that Nvidia highest end GPU dies do. Humongous GPU dies don't have big trade off of capping clock to get more area design ( more cores in same space). It is mostly 'embarrassing parallel' computation trying to do.
If Apple did use N3X on Max die it more likely would be to shrink the die (and package) than to win the single thread drag racing crown among overclocking solutions. Shrinkage of die would put it back in the same situation as being same single threaded as plain Mn have now. All the folks moaning and groaning about mega drag racings are not going to be happy (and spend gobs of extra dollars to buy one). The iGPU will still be integrated so the hyper modular dGPU fans also still won't be happy.