I tried set ARTFrequency, FSBFrequency, InitialTSC manually, but nothing change so far.
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MP 1,1-5,1 Manually Configured OpenCore on the Mac Pro
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I tried set ARTFrequency, FSBFrequency, InitialTSC manually, but nothing change so far.
I compared 2 shots one without spoofing and one with it. The only difference I see is the CPUfrequency min/max reported 3500 instead of 3460 and machdep.cpu.microcode_version: 0 instead of 31.
I wonder if the microcode version will make a difference. I don't see a way to set the microcode version from OC.
No, I don't think MC version will make the difference of clock speed.
However, if MC is not really loaded, then the cMP is subjected to more loophole.
Use debug build of opencore and set it to log to EFI partition then see the log after you boot.
What if we set ARTFrequency lower with the same percentage as what exists between greped frequency and the reported from OCPU?
ART Frequency, CPU Frequency and Clock Drift · Issue #448 · acidanthera/bugtracker
OCCPU is misreporting my CPU's frequency. I believe it's also causing the macOS system clock to run fast: 00:226 00:113 OCCPU: Found Intel(R) Xeon(R) Gold 6136 CPU @ 3.00GHz 00:345 00:118 OCCPU: Si...
github.com
Add cpuid hypervisor support to work with virtualization by Leoyzen · Pull Request #17 · acidanthera/OcSupportPkg
acidanthera/bugtracker#531 For some reason that some msr not impletement in such hypervisor (QEMU/KVM/VMWare), so some logic may not work fine in a VM. This commit will add cpuid hypervisor support...
github.com
Last edited:
What if we set ARTFrequency lower with the same percentage as what exists between greped frequency and the reported from OCPU?
ART Frequency, CPU Frequency and Clock Drift · Issue #448 · acidanthera/bugtracker
OCCPU is misreporting my CPU's frequency. I believe it's also causing the macOS system clock to run fast: 00:226 00:113 OCCPU: Found Intel(R) Xeon(R) Gold 6136 CPU @ 3.00GHz 00:345 00:118 OCCPU: Si...
Add cpuid hypervisor support to work with virtualization by Leoyzen · Pull Request #17 · acidanthera/OcSupportPkg
acidanthera/bugtracker#531 For some reason that some msr not impletement in such hypervisor (QEMU/KVM/VMWare), so some logic may not work fine in a VM. This commit will add cpuid hypervisor support...
TBH, I don't think there will be any effect. I tried different numbers a few times, seems no effect at all. May be I can't find the magic number yet, therefore, OC fall back to some default failsafe setting.
Apparently you have never dealt with a bunch of clowns like them before, some of the most ignorant I have ever had the misfortune to run across.
You can probably get started with the instructions in the first post. However, as explained in post #459, you may have to consider SMBIOS spoofing instead of the VMM flag.
Yeap some of them exhibit unbearable level of arrogance.
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And when you ask a question in the forum (insanelymac) you get no answers.
Aaha, I think I found how can we fix the microcode revision:
All we have to do is Cpu->Vendor[0] == CPUID_VENDOR_INTEL (If we can set it. If not why is it not reading INTEL?)
So it is reading register AsmReadMsr32.
Maybe we dig for the frequency mismatch?
Code:
if (Cpu->Vendor[0] == CPUID_VENDOR_INTEL) {
Cpu->MicrocodeRevision = AsmReadMsr32 (MSR_IA32_BIOS_SIGN_ID);
}
Cpu->Signature = Cpu->CpuidVerEax.Uint32;
Cpu->Stepping = (UINT8) Cpu->CpuidVerEax.Bits.SteppingId;
Cpu->ExtModel = (UINT8) Cpu->CpuidVerEax.Bits.ExtendedModelId;
Cpu->Model = (UINT8) Cpu->CpuidVerEax.Bits.Model | (UINT8) (Cpu->CpuidVerEax.Bits.ExtendedModelId << 4U);
Cpu->Family = (UINT8) Cpu->CpuidVerEax.Bits.FamilyId;
Cpu->Type = (UINT8) Cpu->CpuidVerEax.Bits.ProcessorType;
Cpu->ExtFamily = (UINT8) Cpu->CpuidVerEax.Bits.ExtendedFamilyId;
Cpu->Brand = (UINT8) Cpu->CpuidVerEbx.Bits.BrandIndex;
Cpu->Features = (((UINT64) Cpu->CpuidVerEcx.Uint32) << 32ULL) | Cpu->CpuidVerEdx.Uint32;
if (Cpu->Features & CPUID_FEATURE_HTT) {
Cpu->ThreadCount = (UINT16) Cpu->CpuidVerEbx.Bits.MaximumAddressableIdsForLogicalProcessors;So it is reading register AsmReadMsr32.
Maybe we dig for the frequency mismatch?
This is how the Westmere is handled:
Code:
// Calculate the Tsc frequency
//
Cpu->TSCFrequency = GetPerformanceCounterProperties (NULL, NULL);
if (Cpu->CPUFrequency == 0) {
//
// There may be some quirks with virtual CPUs (VMware is fine).
// Formerly we checked Cpu->MinBusRatio > 0, but we have no MinBusRatio on Penryn.
//
if (Cpu->TSCFrequency > 0 && Cpu->MaxBusRatio > Cpu->MinBusRatio) {
Cpu->FSBFrequency = DivU64x32 (Cpu->TSCFrequency, Cpu->MaxBusRatio);
Cpu->CPUFrequency = MultU64x32 (Cpu->FSBFrequency, Cpu->MaxBusRatio);
} else {
Cpu->CPUFrequency = Cpu->TSCFrequency;
Cpu->FSBFrequency = 100000000;
}
}
//
........
} else if (Cpu->Model == CPU_MODEL_WESTMERE) {
Msr = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
Cpu->CoreCount = (UINT16)BitFieldRead64 (Msr, 16, 19);
Cpu->ThreadCount = (UINT16)BitFieldRead64 (Msr, 0, 15);
} else {
Msr = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
Cpu->CoreCount = (UINT16)BitFieldRead64 (Msr, 16, 31);
Cpu->ThreadCount = (UINT16)BitFieldRead64 (Msr, 0, 15);
}
if (Cpu->CoreCount == 0) {
Cpu->CoreCount = 1;
}
if (Cpu->ThreadCount == 0) {
Cpu->ThreadCount = 1;
}
//
// TODO: handle package count...
//
}And here are the calculations when manually entered in the data hub:
Smbios section
Code:
DataHubSetAppleMiscAscii (DataHub, OC_PLATFORM_NAME, Data->PlatformName);
DataHubSetAppleMiscUnicode (DataHub, OC_SYSTEM_PRODUCT_NAME, Data->SystemProductName);
DataHubSetAppleMiscUnicode (DataHub, OC_SYSTEM_SERIAL_NUMBER, Data->SystemSerialNumber);
if (Data->SystemUUID != NULL) {
//
// Byte order for SystemId must be swapped.
//
CopyGuid (&SystemId, Data->SystemUUID);
SystemId.Data1 = SwapBytes32 (SystemId.Data1);
SystemId.Data2 = SwapBytes16 (SystemId.Data2);
SystemId.Data3 = SwapBytes16 (SystemId.Data3);
DataHubSetAppleMiscData (DataHub, OC_SYSTEM_UUID, &SystemId, sizeof (SystemId));
}
DataHubSetAppleMiscAscii (DataHub, OC_BOARD_PRODUCT, Data->BoardProduct);
DataHubSetAppleMiscData (DataHub, OC_BOARD_REVISION, Data->BoardRevision, sizeof (*Data->BoardRevision));
DataHubSetAppleMiscData (DataHub, OC_STARTUP_POWER_EVENTS, Data->StartupPowerEvents, sizeof (*Data->StartupPowerEvents));
DataHubSetAppleProcessorData (DataHub, OC_INITIAL_TSC, Data->InitialTSC, sizeof (*Data->InitialTSC));
if (Data->FSBFrequency == NULL) {
Data->FSBFrequency = &CpuInfo->FSBFrequency;
}
DataHubSetAppleProcessorData (DataHub, OC_FSB_FREQUENCY, Data->FSBFrequency, sizeof (*Data->FSBFrequency));
DataHubSetAppleProcessorData (DataHub, OC_ART_FREQUENCY, Data->ARTFrequency, sizeof (*Data->ARTFrequency));
DataHubSetAppleMiscData (DataHub, OC_DEVICE_PATHS_SUPPORTED, Data->DevicePathsSupported, sizeof (*Data->DevicePathsSupported));
DataHubSetAppleMiscData (DataHub, OC_SMC_REVISION, Data->SmcRevision, OC_SMC_REVISION_SIZE);
DataHubSetAppleMiscData (DataHub, OC_SMC_BRANCH, Data->SmcBranch, OC_SMC_BRANCH_SIZE);
DataHubSetAppleMiscData (DataHub, OC_SMC_PLATFORM, Data->SmcPlatform, OC_SMC_PLATFORM_SIZE);
return EFI_SUCCESS;
}
© 2019 GitHub, Inc.Smbios section
According to the above code
Code:
if (Data->FSBFrequency == NULL) {
Data->FSBFrequency = &CpuInfo->FSBFrequency;So you said if you apply 133 there nothing changes? Shouldn't default be 133x26 (for x5690)?
>>>>>nvram boot-args="-no_compat_check"
Is this Catalina solution.. always need a bootable Mojave drive as standby to add this parameter back when the NVRAM is reset?
Is this Catalina solution.. always need a bootable Mojave drive as standby to add this parameter back when the NVRAM is reset?
If you do everything as per post #1 (Enable boot entry preservation, no compat check argument is included in the config.plist), and your OpenCore drive is the very first macOS drive that the cMP can locate after NVRAM reset... then you cMP will still automatically boot to Catalina via OpenCore after NVRAM reset. I tested that on my own cMP. It works.
In my case, it's a SATA SSD on my TempoSSD card.
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I tried all possible values that I can think of, nothing changed so far.
I'm not sure if the procedure in Post#1 5a, after the reboot. My dual Xeon Mac Pro 2010 could never boot into recovery mode unless I remove the drive that with EFI/Opencore modified. Is there any trick to get it work on a dual CPUs system?
Have you tried Command (⌘)-R at boot? Just be patient there is a lot of wait...
Also make your scan policy 0 (all drives and partitions).
The procedure in post #1 was developed with a dual-processor machine. Step 5a should work as described.
This is to acknowledge that I have just lost my bootdrive after applying the Opencore. I've removed it from EFI partition and reset the NVRAM. All data in the drive is still accessible thru another boot drive mounted externally, so I could still rescue all data in it.
I understand this thing is under experimental development and I don't blame anyone who contributes to this. Just want to say this thing is unsafe for now under dual boot configuration. Some boot parameters could be fatally damaged during booting A <-> B drive configuration thru the NVRAM. Even resetting the NVRAM wouldn't help. Make sure you have a backup copy before proceeding anything on this thing.
Keep up good work.
I understand this thing is under experimental development and I don't blame anyone who contributes to this. Just want to say this thing is unsafe for now under dual boot configuration. Some boot parameters could be fatally damaged during booting A <-> B drive configuration thru the NVRAM. Even resetting the NVRAM wouldn't help. Make sure you have a backup copy before proceeding anything on this thing.
Keep up good work.
To all the experts on this thread!! Especially Alex! I am a real newbie and want to install Catalina utilizing the Open-Core method. I am willing to follow Cdf post 1 exactly- Of course I realize I could "Brick" my machine because I Know Nothing about Open-Core! Any tips will be sooo welcome! I have copied all the post 1 updates so far- and will start with this last update-
I do not understand what you all have been discussing regarding the last several pages of the thread at all- Do they matter if I follow the steps exactly in Post 1??? Thanks for any info.! Will report what happens-
My machine is a 4,1 to 5,1 cMP dual processor X5690 12 core with a GTX 680 and a (7101A working 2 Samsung NVMe drives Thanks To Alex!!
I do not understand what you all have been discussing regarding the last several pages of the thread at all- Do they matter if I follow the steps exactly in Post 1??? Thanks for any info.! Will report what happens-
My machine is a 4,1 to 5,1 cMP dual processor X5690 12 core with a GTX 680 and a (7101A working 2 Samsung NVMe drives Thanks To Alex!!