RISC-V getting closer to come to Apple silicon?

[leman]

Ventana yesterday unveiled Veyron v2, a 15-width out-of-order processor. It would be the widest processor, wouldn't it?

Ventana Introduces Veyron V2 — World’s Highest Performance Data Center-Class RISC-V Processor and Platform - Ventana Micro

Ventana Micro Systems Inc. today announced the second generation of its Veyron family of RISC-V processors. The new Veyron V2 is the highest performance RISC-V processor available today and is offered in the form of chiplets and IP.

www.ventanamicro.com

Depends of what and how they count. I was not able to find any concrete performance numbers, but their veyron v1 is claimed to achieve up to 6 points in SPECint2017. With 40% higher v2 should be around 8.5 points, which is around M2 performance. I would honestly be very impressed if they can indeed deliver it.

 

[Xiao_Xi]

STH offers a little more information on the Veyron V2, but the report seems to be based on Ventana's commercial presentation and not on the technical presentation of the Veyron V2 at the RISC-V Summit.

Ventana Veyron V2 RISC-V CPU Launched for the DSA Future

The Ventana Veyron V2 is a 192-core RISC-V server CPU designed for UCIe compute chiplets and domain-specific accelerator silicon integration

www.servethehome.com

 

[Xiao_Xi]

A comparison between Armv-8a and rv64gc has recently been published.

An Empirical Comparison of the RISC-V and AArch64 Instruction Sets | Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

dl.acm.org

 

[Basic75]

A comparison between Armv-8a and rv64gc has recently been published.

An Empirical Comparison of the RISC-V and AArch64 Instruction Sets | Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

dl.acm.org

They should have included ARM with NEON, too. The pure scalar results are interesting from a theoretical perspective, but if all modern ARM chips support NEON then they don't reflect what you can expect in the real world.

 

[leman]

A comparison between Armv-8a and rv64gc has recently been published.

An Empirical Comparison of the RISC-V and AArch64 Instruction Sets | Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis

dl.acm.org

It’s not really a comparison between the ISAs but a study of ILP limits in an ideal processor. I don’t think their conclusions are applicable to real world CPUs.

For example, where their ideal processor sees a serial dependency and thus breaks the parallel execution, a real processor will often fuse instructions into a single dependency-breaking operation. Already this makes their conclusions moot.