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RISC-V getting closer to come to Apple silicon?
- Thread starter jz0309
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Finally managed to watch it, a fascinating talk and easy enough to understand for someone without a background in CPU design.
Although I’m not quite sure what this has to do with RISC-V? In the end they modify the ISA so heavily that almost nothing is left…
RISC-V is open source, which of course makes it a prime candidate if you are in academia and want to start with something already there. What I mean is that the talk does not make any arguments in favour of RISC-V, it simply discusses a way to design an energy-efficient domain-specific accelerator.
SVE2 is optional so far in the early v9 sequence. That doesn't mean it will be optional by the end.
I don't think the arch licenses are doled out on a 'dot' granularity. ( buy 9.2 but not 9.6 and every time Arm does another x.(y+1) have to write another check). Payments on the overall 9 could be spread out , but it isn't a 'nickel and dime' exercise). Stuff that is optional at x.1 , x.2. , x.3 isn't necessarily optional at x.5 , x.6, x.7
By the time Arm gets to the end of v9 updates there is probably no good reason for it not to be pragmatically required for everything that isn't some niche embedded controller. If enough implementers do it , defacto needed for portable code.
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ARM themselves has yet to design an SVE2 (or even SVE) capable core. There is only one implementation of SVE so far: the Fugaku supercomputer; the AWS Graviton3 is supposed to have it, if it has been deployed yet. I have not yet checked, but I do not believe nVidia's Grace cores even have it.
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I think your info is a bit outdated? SVE2 is supported on majority of ARMs current performance-focused designs, both on server and consumer.
Doesn't match up with Arm's documentation.
" ...
The Cortex®‑X2 core supports the Scalable Vector Extension (SVE) and the Scalable Vector Extension 2 (SVE2). SVE and SVE2 complement and do not replace AArch64 Advanced SIMD and floating-point functionality.
SVE is an optional extension introduced by the Armv8.2 architecture. SVE is supported in AArch64 state only. SVE provides vector instructions that, primarily, support wider vectors than the Arm Advanced SIMD instruction set.
The Cortex®‑X2 core implements a scalable vector length of 128 bits. ...
"
Documentation – Arm Developer
developer.arm.com
[ X2 is in Dimensity 9000 , Snapdragon 7+ gen 2 and 8+ Gen 1 , Exynos 2200
upcoming Google Tensor 3 reportedly has an X3 core in it. ( X3 is just a superset of X2 ) ]
Graviton 3 has SVE1 and has been deployed for a while.
New – Amazon EC2 C7g Instances, Powered by AWS Graviton3 Processors | Amazon Web Services
I am excited to announce that Amazon Elastic Compute Cloud (Amazon EC2) C7g instances powered by the latest AWS Graviton3 processors that have been available in preview since re:Invent last year are now available for all. Let’s decompose the name C7g: the “C” instance family is designed for...
AWS Graviton3 Hits GA with 3 Sockets Per Motherboard Designs
Amazon AWS Graviton3 C7g instances are now in GA and are built upon a 3 CPU per motherboard design which is very unique
These don't have many license implementators yet, but the pipeline is coming:
Neoverse N2 and V2 have SVE2
In particular Nvidia Grace
" Neoverse V2 Cores: Armv9 with 4x128b SVE2 ..."
NVIDIA Grace CPU Superchip Architecture In Depth | NVIDIA Technical Blog
The NVIDIA Grace CPU Superchip brings together two high-performance and power-efficient NVIDIA Grace CPUs with server-class LPDDR5X memory connected with NVIDIA NVLink-C2C.
P.S. the 'prize' the Fujitsu Fugaku still owns is vector length 512. I don't think anyone has tried to match that yet.
P.P.S. The 510 and 710 also
" ... The Cortex-A510 is the first small core from Arm to feature the Armv9 ISA along with the Scalable Vector Extension (SVE) and SVE2 extensions. ..."
Cortex-A510 - Microarchitectures - ARM - WikiChip
Cortex-A510 (codename Klein) is an ultra-high efficiency microarchitecture designed by ARM Holdings as a successor to the Cortex-A55. The Cortex-A510, which implements the ARMv9.0 ISA, is typically found in smartphone and other embedded devices. Often A510 cores are combined with higher...
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One has to note however that A64FX is a very specialized design that is dead slow on general-purpose code. It’s pretty much a vector processing machine where everything revolves around its 2x512bit FP SIMD.
Qualcomm has shared a pdf with more slides, where it explains it.
You can follow the conversation on the mailing list
Qualcomm slides on C extension, part 2
Qualcomm has shared a pdf with more slides, where it explains it.
View attachment 2290252
You can follow the conversation on the mailing list
Qualcomm slides on C extension, part 2
lists.riscv.org
Right, so they basically copied all the good stuff from ARMv8. This actually makes RISC-V a competent ISA (of course, they’d still need to introduce more compute-oriented functionality).
Asanovic, one of the creators of RISC-V, has prepared a presentation to defend the extension to C.
lists.riscv.org
Slides on retaining IALIGN=16 for RVA profiles
Asanovic, one of the creators of RISC-V, has prepared a presentation to defend the extension to C.
Slides on retaining IALIGN=16 for RVA profiles
I think this is a very interesting dialogue because it shows very clearly where different parties see their priorities. Qualcomm is interested in high-performance computing and their suggestions aim to close certain deficiencies in RISC-C that make high-performance computing a challenge. On the other hand, Asanovich represents the group that cares more about simple processors and low complexity implementations rather than high-performance computing. Incidentally, this was the impression I always had about RISC-V, so it’s interesting to have a confirmation from the source.
In the end, I wouldn’t be surprised if Qualcomm rolls their own extension anyway (with or without the group’s blessing), and it’s likely that other companies who actually care about performance will join them. So we might end up with multiple strictly separated dialects of RISC-V that require different compiler backends.
For what its worth, I think that Qualcomm is right, and that their suggestion is much better than “just fuse instructions” proposal that dominated RISC-V until then.
Qualcomm favors cracking over fusion instruction.
Re: Qualcomm Slides on C extension
The plot thickens and gets more and more interesting. Qualcomm has refuted SiFive's arguments and it appears that some of the new ideas run so counter to the initial RISC-V vision that Andrew Waterman, one of the creators of RISC-V, has stated:
lists.riscv.org
Re: Padding with 64-bit naturally-aligned instructions
But , but , but profiles perfectly handles all of this Balkanization stuff.... *cough*
Can you see it now? It has been there for a long while now.
Do you mean Qualcomm is against every other company? Some people on Reddit believe that Qualcomm is pushing to get rid of the C extension to make RISC-V look more like ARM, so they can reuse their ARM cores.
Edit: I don't deny that you may be right and that profiles don't solve the problem of extensions, but I think you have based your reasoning on a hunch and not on evidence. I would consider that profiles don't serve their purpose if Linux applications and distros aren't compiled using the corresponding profile.
By the way, the word Balkanization brings back terrible memories for Europeans. So unless you think these companies are going to kill each other like the people in those countries did, you should find a better metaphor.
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And while we are discussing the future of RISC-V, it looks like SiFive, one of the most influential companies in the space, has instigated mass layoffs. Can't say I am surprised, I never really understood their business model or goals. Still, this will likely be a major setback for the public perception of RISC-V. It is possible that none of the advanced SiFive designs will actually enter the general market.
Curious what Tenstorrent Ascalon will deliver at this point.
Curious what Tenstorrent Ascalon will deliver at this point.
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Ian Cutress got confirmation from SiFive.
SiFive's opening position seems suspicious. It is possible that SiFive is focusing more on its Indian office than on the American ones. In any case, it doesn't look good for either SiFive or RISC-V.
Careers at SiFive - Make an Impact Today & Define Tomorrow
SiFive is championed by leaders who chose to make a real difference. We led the RISC-V revolution & now you have the opportunity to write the future with us. Don't just watch the future unfold. Help us lead the way.
www.sifive.com
SiFive has been 'influx' for a while.
They spun out part of the company last year for ~ $200M .
" ... Alphawave will be acquiring a 300+ person team from the California-based firm, located primarily in India. ..."
Note the size there is in the same range as the size been whispered as the current layoff size ( 100-300 ).
" ...
through multiple sources, SiFive has instigated a large number of layoffs. Numbers vary, from 100 to 300+, but multiple sources confirm that most of the engineering team, especially the physical design engineers, sales, and product team. The management team have also been fired from what I've been told, ..."
SiFive physical products have been kind of 'odd' for a long while. They'd talk about releasing demo boards but it would almost be like a kickstarter projects. It would wonder around for a while in pre-release. Then they would distribute some. And then it would be "oh the next board is so exciting we aren't going to make any more of these current ones so can focus on the next one. " Rinse and repeat.
If look at the range of vendors doing RISC-V development boards
https://riscv.org/risc-v-developer-boards/
If RISC-V goes from 8 to 7 options for boards that isn't much of a loss. In fact, might actually be healthier ecosystem. "StarFive" ( similar sounding name) is a chinese vendor
But it is kind of a long way from Intel tossing around the idea of spending $2B on them. Likely would have been $2B wasted by Intel that they sorely need now to cover other Intel 'bets' that went sideways. There could have been a problem if SiFive went off and did something relatively expensive to encourage Intel to buy them out and then it fell through ( e.g. spin up a fancy Intel fabbed chip that never went on sale in substantive numbers. )
The 'other half' of SiFive wanted to run an Arm-like model where they primarily just license IP. This may not mean very much for Tenstorrent as they likely still have whatever IP they licensed from SiFive.
The problem for SiFive is that many vendors in the embedded controller market are drifting away from Arm in part because of the licensing model. So SiFive copying that aspect.... is a bit dual edged. SiFive is more so going to be a 'significant subcontractor' on designs than then the primary contractor role that Arm plays in many cases . They aren't going to have that kind of pricing power.
That is bad if the VC investors expect them to be the 'next Arm' . It just isn't practical. This layoff looks like one of those inflection points when the money folks start to come back to reality of what they actually have as opposed to what they wished they had.
Ventana yesterday unveiled Veyron v2, a 15-width out-of-order processor. It would be the widest processor, wouldn't it?
www.ventanamicro.com
I hope that Ventana's presentation will soon be available on Youtube.
Ventana Introduces Veyron V2 — World’s Highest Performance Data Center-Class RISC-V Processor and Platform - Ventana Micro
Ventana Micro Systems Inc. today announced the second generation of its Veyron family of RISC-V processors. The new Veyron V2 is the highest performance RISC-V processor available today and is offered in the form of chiplets and IP.
www.ventanamicro.com
I hope that Ventana's presentation will soon be available on Youtube.
Correct me if I'm wrong, if 15 is the decode and dispatch width that would be impressive and unprecedented, but if it's just the total number of execution units not so much.