RISC-V getting closer to come to Apple silicon?

[ChrisA]

Report: Apple to Move a Part of its Embedded Cores to RISC-V, Stepping Away from Arm ISA | TechPowerUp}

www-techpowerup-com.cdn.ampproject.org

Interesting move

RISC-V has some advantage in the areas are processor sell at the $1 and $2 price point. I have some chips here on my desk and I can say that the $4 dual-core RISC-V seriously outperforms the $1 dual-core ARM. The ARM chip is phyically smaller and uses less power. But I can find other ARMS that are fester then the RISC-V.

Comparing ARM vs. RISC-V is like comparing Ford vs. Chevy. It is silly. You have to compare a specific model to a specif model, not company to company. Each company make a full range of cars. Then, when you do that, you find some models from each company beat the others and vice versa.

Next, the funny thing about embedded processor is that many times you end up using the slower chip because the slower chip uses less power and space and a faster chip would just have more idle time.

 

[dmccloud]

But what does the license allows and disallows.

I was watching this video on the Qualcomm/Nuvia vs ARM lawsuit and thought to myself what can Apple do or not do with their ARM license/contract?

This includes legal commentary from @ServeTheHomeVideo who happens to be a JD.

Two completely separate licenses. Qualcomm licenses ARM designs (cores) and integrates those into their SoCs. Apple licenses the ISA itself, and designs it's SoCs entirely in-house. In fact, Apple has already built their own additions on top of the existing ARM ISA, some of which have been backported into the ARM ISA itself.

 

[Xiao_Xi]

The ARM chip is phyically smaller and uses less power.

Aren't more performance/area and more efficiency/area two of the advantages of RISC-V over ARM on small cores?

 

[leman]

Aren't more performance/area and more efficiency/area two of the advantages of RISC-V over ARM on small cores?

Why would it have this kind of advantage? One of the main point of RISC-V as I see it that it’s very simple to implement. So if you want a very small, low-power core that doesn’t really care much for performance, RISC-V is amazing (especially since you can drop things like atomics and floating point if you don’t need them, and there is no SIMD to begin with). But if you want really fast core, RISC-V ISA starts to put sticks in your wheels.

 

[Xiao_Xi]

Why would it have this kind of advantage?

Sifive's marketing documentation states:

SiFive Performance™ P400

The SiFive Performance P450/470-Series application processors are SiFive’s first efficiency-focused Out-of-Order processors.

www.sifive.com

 

[Sydde]

Cortex-A55? A core design that was released six years ago and has not really been put into SoCs since '18? That seems like some weak tea.

 

[poorcody]

I think any move by Apple to RISC-V would be more business motivated than technological. I can't help think they must have been spooked when Nvidia made a move to buy ARM. Their dislike (to put it mildly) of Nvidia is almost apocalyptic. Whatever favorable license terms Apple may have, Apple doesn't want to deal with them or anyone similar. It's is in Apple's DNA to transition everything in-house anyway.

Given Apple's R&D budget, they may just be researching the potential of the CPU at this stage (and to hedge their bets). But I bet you there is a RISC-V based system running a port of MacOS and iOS somewhere in the Spaceship.

 

[leman]

Sifive's marketing documentation states:

SiFive Performance™ P400

The SiFive Performance P450/470-Series application processors are SiFive’s first efficiency-focused Out-of-Order processors.

www.sifive.com

I am not familiar with any of these products, but a cursory glance shows that P470 has three integer execution units and runs at 3ghz while A55 has two int units and in this particular comparison runs at 1.9ghz. So I’m not surprised that the first one is considerably faster in an integer benchmark. And I’m also not surprised that P470 is smaller, it has fewer floating point units. Just as Sydde said, I find it a bit strange that they decided to compare their product to a core released in 2017 instead of a more recent design.

And finally, I’m also curious about the power consumption. This is something notably absent from the slides and I have some difficulty believing a core running at 3ghz will use less power than one running at 2ghz.

 

[Sydde]

I have some difficulty believing a core running at 3ghz will use less power than one running at 2ghz

If the P470 was made in the past 6 months, it probably would have been on something like TSMC's N5 process – Cortex-A55s are most likely on N7 or larger. A decently built processor will be able to run faster while pulling less juice when burned on a smaller node.

 

[Basic75]

Apple might be throwing most of their hypervisor/virtualization work down the toilet , but it is an option to shift to an walled garden with even higher, ’20m’ walls .

If they switch to a custom ISA it's not just Bootcamp that goes down the drain. They would be pissing off a lot of developers and power users by killing Linux VMs and they know it. After all, they put some real effort into making Linux on ARM Macs run well, including making Rosetta 2 available to transalte Linux executables in virtual machines.

 

[leman]

If the P470 was made in the past 6 months, it probably would have been on something like TSMC's N5 process – Cortex-A55s are most likely on N7 or larger. A decently built processor will be able to run faster while pulling less juice when burned on a smaller node.

The slides seem to suggest that the comparison was done at 7nm.

 

[Xiao_Xi]

Cortex-A55? A core design that was released six years ago and has not really been put into SoCs since '18? That seems like some weak tea.

The comparison may be related to one of Qualcomm's SoCs. Four months before Sifive announced the P470, Qualcomm announced the Snapdragon W5+ Gen 1, a SoC using 4xA53.

Qualcomm Launches Snapdragon W5+ and W5 Platforms for Next Generation Wearables: Our Most Advanced Leap Yet | Qualcomm

Qualcomm is launching the Snapdragon W5+ and W5 platforms for next-generation wearables, offering advanced performance and advanced connectivity capabilities.

www.qualcomm.com

SiFive’s New High-Performance Processors Offer a Significant Upgrade for Wearable and Consumer Products

www.sifive.com

 

[leman]

The comparison may be related to one of Qualcomm's SoCs. Four months before Sifive announced the P470, Qualcomm announced the Snapdragon W5+ Gen 1, a SoC using 4xA53.

Qualcomm Launches Snapdragon W5+ and W5 Platforms for Next Generation Wearables: Our Most Advanced Leap Yet | Qualcomm

Qualcomm is launching the Snapdragon W5+ and W5 platforms for next-generation wearables, offering advanced performance and advanced connectivity capabilities.

www.qualcomm.com

SiFive’s New High-Performance Processors Offer a Significant Upgrade for Wearable and Consumer Products

www.sifive.com

If SiFive can manage to achieve that performance at the same power usage as an A55 running at 2Ghz I would be very impressed. But somehow I suspect that they are using peak performance in their marketing materials and the actual products for wearables are going to be much more conservatively clocked.

 

[Xiao_Xi]

a cursory glance shows that P470 has three integer execution units and runs at 3ghz while A55 has two int units and in this particular comparison runs at 1.9ghz. So I’m not surprised that the first one is considerably faster in an integer benchmark. And I’m also not surprised that P470 is smaller, it has fewer floating point units.

Out of curiosity, how do you know how many floating point and integer units each core has?

 

[leman]

Out of curiosity, how do you know how many floating point and integer units each core has?

It’s there in the slides you have linked. For A55 there is a nice article here: https://www.anandtech.com/show/11441/dynamiq-and-arms-new-cpus-cortex-a75-a55/4

 

[Xiao_Xi]

It’s there in the slides you have linked.

I'm lost in all the jargon. I can imagine that P470 has a floating unit because it has a vector ALU, but I can't figure out how you know it has three integer units.

If SiFive can manage to achieve that performance at the same power usage as an A55 running at 2Ghz I would be very impressed.

Aren't out-of-order cores, such as the P470, more efficient than in-order cores, such as the A55?

 

[Sydde]

The Cortex-A55 is also ARMv8, which means it supports AArch32 (including Thumb2) as well as AArch64. This will make its die slightly larger. A better comparison might be A510, which is v9 and can only use AArch64.

 

[Xiao_Xi]

better comparison might be A510, which is v9 and can only use AArch64.

Although a comparison with the A510 seems fairer on paper, there must be something that made Samsumg and Qualcomm not use the A510 for their wearable SoC. Qualcomm's Snapdragon W5+ uses the A53 and Samsung's Exynos W920 uses the A55. So it makes sense for SiFive to make the comparison to the A55/A53 because that is the core that is used for wearable SoCs.

By the way, last month Luca Benini gave a very interesting talk on tricks to improve the efficiency of cores.

 

[altaic]

Although a comparison with the A510 seems fairer on paper, there must be something that made Samsumg and Qualcomm not use the A510 for their wearable SoC. Qualcomm's Snapdragon W5+ uses the A53 and Samsung's Exynos W920 uses the A55. So it makes sense for SiFive to make the comparison to the A55/A53 because that is the core that is used for wearable SoCs.

By the way, last month Luca Benini gave a very interesting talk on tricks to improve the efficiency of cores.

Thanks for the link to Benini’s talk. Really interesting. Wish he had an hour or more; he was moving at a tremendous clip.

 

[deconstruct60]

If they switch to a custom ISA it's not just Bootcamp that goes down the drain. They would be pissing off a lot of developers and power users by killing Linux VMs and they know it. After all, they put some real effort into making Linux on ARM Macs run well, including making Rosetta 2 available to transalte Linux executables in virtual machines.

There isn't an actively supported "Bootcamp" now. That isn't primarily an ISA issue.

Depending upon where Apple forks off it wouldn't be completely custom. Arm 9 added in more robust virtualization support. If Apple tracks a coherent subset of the current 9.x instruction set, then the version of Linux tracking future older servers will pick up Apple's ISA also.

( e.g., how many Linux distros still keeping up with 32-bit x86. Basically the same thing ( Rosetta 2 dosn't cover 32 x86 , but is targeting slow moving/evolving x86_64 code in Linux that doesn't have an Arm recompile/port yet.). Very slow moving code tends not to adopt new ISA features quickly. Over a very long protracted amount of time that would get more stressed as more server workloads adopted new Arm ISA features. But if Arm was suffering in competition with RISC-V and x86 that would be a slower slide into a problematically zone. )

There is difference between completely custom and just quitting because don't see any value add in the additional instructions.

ARM is adding some instructions to do more efficient VM nesting and hypervisor features , but can still run a virtualization/hypervisor without hardware assistance ... it is just much slower.

As ARM gets to v10 , v11 , v12 of the ISA the new features are likely going to be even more fringe and narrowly focused. What the vast majority of apps needs is already there in v9.

 

[Sydde]

If Apple tracks a coherent subset of the current 9.x instruction set, then the version of Linux tracking future older servers will pick up Apple's ISA also.

There are no base instructions added in v9. It adds SVE2, but that remains optional. Mosty, 9 adds new security domain architecture and makes AArch32 optional.

 

[Xiao_Xi]

Would it make sense for Apple to use RISC-V based accelerators for cloud computing like Meta does?

https://dl.acm.org/doi/10.1145/3579371.3589348

 

[Sydde]

Not particularly. Apple has farmed a large fraction of their ML workload out to client devices, so their cloud stuff is not all that elaborate. Apple is largely not quite as heavily focused on targeted marketing the way Meta is: their needs are not the same. And anyway, RISC-V does not have any particular advantage over ARM in this area. When you already have the architecture license, RISC-V has very little to offer.

 

[dmccloud]

Would it make sense for Apple to use RISC-V based accelerators for cloud computing like Meta does?

https://dl.acm.org/doi/10.1145/3579371.3589348

Apple isn't in the business of collecting every piece of personal data and then analyzing/selling it like Meta is. For that reason alone, Apple does not need the same infrastructure as Meta. Apple also places an emphasis on customer data remaining private unless needed (i.e., making a purchase through the App Store, AppleTV, Apple Music). Meta takes the opposite approach and views the data as their product while Facebook, Instagram, and now Threads are just data mining tools used to collect such information.

 

[Xiao_Xi]

Apple isn't in the business of collecting every piece of personal data and then analyzing/selling it like Meta is. For that reason alone, Apple does not need the same infrastructure as Meta.

Just because Apple conducts experiments to collect data doesn't mean it doesn't need a large infrastructure to train its models. How do you think Apple trains its models?