Rumored pro chip

[senttoschool]

I understand binning. Show me where Gurman confirmed that we’re going to have 10, 16, 18, 20 core chips.

I’m not saying it’s not going to happen but Gurman didn’t confirm this. All he said was we would get a 10-core, 20-core, and 40-core chip. He didn’t mention binning. So all of that is just guesswork. Not confirmed.

For the new MacBook Pros, Apple is planning two different chips, codenamed Jade C-Chop and Jade C-Die: both include eight high-performance cores and two energy-efficient cores for a total of 10, but will be offered in either 16 or 32 graphics core variations.

Codenamed Jade 2C-Die and Jade 4C-Die, a redesigned Mac Pro is planned to come in 20 or 40 computing core variations, made up of 16 high-performance or 32 high-performance cores and four or eight high-efficiency cores. The chips would also include either 64 core or 128 core options for graphics. The computing core counts top the 28 core maximum offered by today’s Intel Mac Pro chips, while the higher-end graphics chips would replace parts now made by Advanced Micro Devices Inc.

Apple Readies MacBook Pro, MacBook Air Revamps

Apple Inc. is preparing to release several new Mac laptops and desktops with faster processors, new designs and improved connectivity to external devices, accelerating the company’s effort to replace Intel Corp. chips and leapfrog rival PC makers.

www.bloomberg.com

He confirmed 10/20/40 core chips. I said we can expect Apple to bin 6, 8, 12, 16, 18 core SoCs or something similar depending on defect rates.

You said Apple won’t. I disagreed.

 

[Jorbanead]

You said Apple won’t. I disagreed.

I never said Apple wouldn’t, but I’m simply stating that what you said is all guesswork and not rooted in any information we have. The whole reason I responded to you was because you said this:

First, there will be a lot more binning options on Macs. (4 core, 6 core, 8 core, 10 core, and all the way up to 32 cores according to Bloomberg). There are no SoC options for iPhones and iPads.

And all I am saying is Bloomberg did not say we would get 4, 6, 8, all the way up to 32 cores. He specifically stated 10, 20, and 40. That's all. I understand your logic, I am just pointing out its guesswork and we don't know exactly how they will bin their chips.

 

[Sydde]

40 cores is pushing starvation limits. Even 20 is closing in on that. 16 CPU cores is probably (WAG) the performance sweet spot, especially if they are vying with the GPU and NN cores for resources. If Apple wants to chase really high performance, they will design optimal flow stackables, each with their own in-package RAM using some sort of UMA interconnect (all subSoCs can reach each other's RAM directly, in a continuous map, but the in-package memory is faster).

 

[richinaus]

Iˋm not sure that we have the same definition of „many“. Just to give you some context, a 32-core CPU using current M1 tech would be close to a 64-core EPYC CPU. Are you trying to tell us that „many people“ need an equivalent of a 256-core AMD server platform?

Apple will target the majority of users as they have previously. Most of us know this and I would advise people to temper expectations to this notion.

 

[Jorbanead]

Apple will target the majority of users as they have previously. Most of us know this and I would advise people to temper expectations to this notion.

The 40-core processors Gurman speaks of is likely a Mac Pro level of chip. Those chips have to at least match current levels of Mac Pro performance, but knowing Apple it would not be unreasonable for them to want to outperform a 28-core Xeon currently offered.

 

[macsplusmacs]

I'd settle for a 37 core.

 

[Appletoni]

I have heard that Apple will increase integer math from 36 MOps/Sec to 180 MOps/Sec and this is great. It’s time to buy the next MacBook Pro too.

 

[leman]

I have heard that Apple will increase integer math from 36 MOps/Sec to 180 MOps/Sec and this is great. It’s time to buy the next MacBook Pro too.

What are you even talking about…

 

[EntropyQ3]

What are you even talking about…

I think it’s satire.
Or, (s)he’s acting like me when people around me talk about Game of Thrones. You, know, trying to participate a bit. (*cough*)
We’re clearly getting a bit silly with numbers here, so…

Maybe getting back on the rails would be an option. Such as - how would you connect these weird-ass 8+2(CPU)+32(GPU) building blocks?

 

[leman]

I think it’s satire.
Or, (s)he’s acting like me when people around me talk about Game of Thrones. You, know, trying to participate a bit. (*cough*)
We’re clearly getting a bit silly with numbers here, so…

I have firmly decided that our local chess crew (Appletoni and co) are incapable of satire (among some other things)

 

[Starfia]

I predict the pro chip will have up to ten trillion efficiency cores per second.

 

[EntropyQ3]

My question at the end was quite serious though.
Partitioning chip functionalities into divisions such as compute dies + I/O die, or CPU + GPU, has been done, and traffic between them has been manageable. The way this rumour is phrased though makes it sound as if the fundamental building block would be 8+2(CPU)+32(GPU) units. Would these connect to an on-package I/O die including global LLC? What would the communication costs be in terms of latencies and power draw? How would this work for graphics workloads, where both nvidia and AMD so far has elected to go with large monolithic chips instead precisely due to communication issues? If you try to alleviate cross chip communication load by putting more of the cache hierarchy on the individual dies, how costly does coherency get?
I can’t balance these issues, I can just see that it hasn’t been done before, and it seems decidedly non-trivial to manage completely transparently, with no drawbacks either in terms of power or performance.

 

[leman]

My question at the end was quite serious though.
Partitioning chip functionalities into divisions such as compute dies + I/O die, or CPU + GPU, has been done, and traffic between them has been manageable. The way this rumour is phrased though makes it sound as if the fundamental building block would be 8+2(CPU)+32(GPU) units. Would these connect to an on-package I/O die including global LLC? What would the communication costs be in terms of latencies and power draw? How would this work for graphics workloads, where both nvidia and AMD so far has elected to go with large monolithic chips instead precisely due to communication issues? If you try to alleviate cross chip communication load by putting more of the cache hierarchy on the individual dies, how costly does coherency get?
I can’t balance these issues, I can just see that it hasn’t been done before, and it seems decidedly non-trivial to manage completely transparently, with no drawbacks either in terms of power or performance.

Well, the way I understand Apples chiplet patent is that they stich multiple chips together, connecting their internal fabrics, essentially making them one monolithic chip. This is different from existing AMD implementation where intra-chiplet communication has to go through the interface die. But that’s just a patent. You never know whether you get to see these things in real life.

Again, I‘m not an engineer and I have very little practical understanding of these things (I did however built a 4-bit CPU from the spare parts of my granpda‘s drawer when I was 12, fun times!). So my speculation and intuition are not worth very much. Still, if I had to guess I‘d say latest industry developments point to stitched chips with external stacked cache. Stitching will combine the chip fabric in a seamless way, and external cache will allow large amount of scalable cache bandwidth.

 

[EntropyQ3]

For clarification, the rumour doesn't say that the top configurations wouldn't be monolithic parts, it's just a hypothesis that has been kicked around. I can't really see why Apple wouldn't opt for a monolithic solution - it would actually seem to reduce design effort and time-to-market for them, and they don't have much interest in spanning over an extremely wide range (whereas AMD for instance uses from half-a-chiplet to eight in their server offerings).

 

[AgentMcGeek]

Did you guys see these allegedly leaked slides from Luke Miani? What do we think?

If production is Q2, I don’t see how we can get a summer launch. However this is in contradiction with other rumours saying production had started in April. Wait & see I guess.

PS: EFI refers to the number of low power cores out of the core total (CPU). Don’t addition CPU and EFI.

 

[reallynotnick]

How does Q2 contradict April? April is the start of Q2.

Also not sure what to make of "upcoming" meaning, like has it been tested or has it yet to be tested?

And are the dates given the dates for when testing starts or are they all target release dates?

Lastly it calls out binning on the smallest chip, weird if they don't bin on the higher end chips too.

 

[AgentMcGeek]

My bad, I had the dates confused on Q2.

As for the upcoming chips, Luke says he believes this is M2 coming later this year to replace M1 in the MBA. But this doesn’t make sense since the list looks like it’s going from most recent to least, as a roadmap should be. Maybe -maybe- this is an outdated slide referring to M1, and turns out they had more defects on the GPU cores than expected.

It may also be that the list isn’t a timeline but rather organised by cores/power/market segmentation. In such case, it could be M2 indeed. Then, why call it a roadmap?

 

[leman]

For clarification, the rumour doesn't say that the top configurations wouldn't be monolithic parts, it's just a hypothesis that has been kicked around. I can't really see why Apple wouldn't opt for a monolithic solution - it would actually seem to reduce design effort and time-to-market for them, and they don't have much interest in spanning over an extremely wide range (whereas AMD for instance uses from half-a-chiplet to eight in their server offerings).

An advanced chiplet solution is probably more rewarding in the long run (higher yields, cheaper production, more configurability), but it also has drawbacks as you rightfully note. Will be interesting to see what Apple goes with in the end.

 

[Sydde]

How does Q2 contradict April? April is the start of Q2

When does FY-Q2 start? December or January?

Either way, the graphic looks pretty ridiculous. Even 40 cores is way too high to be realistic for any package. Apple is not shooting for VY Canis Majoris here. They are primarily making consumer models that will most likely max out at 16, if that, by the middle of the decade. For top-end pro models, they will use some kind of sophisticated PoP configuration that might yield a Mac Pro that is little more than twice the size of the Mac mini (with a pci expansion chassis option).

This stuff we are seeing is just goofball fantasy.

 

[AgentMcGeek]

I’m no expert, but 40 cores on the MacPro doesn’t seem unrealistic if we see 16 cores in a laptop. After all, we’re already seeing Threadrippers and Xeons with several dozen cores, and ARM seems quite scalable…up to a point.

 

[Appletoni]

I’m no expert, but 40 cores on the MacPro doesn’t seem unrealistic if we see 16 cores in a laptop. After all, we’re already seeing Threadrippers and Xeons with several dozen cores, and ARM seems quite scalable…up to a point.

AMD Ryzen 9 3950X 16 cores (105 watt) in a laptop. AMD will increase to 32 cores later.
Apple can sell 40 CPU cores in a MacBook Pro.
I will buy the MacBook Pro 16-inch even with 128 cores.

 

[Appletoni]

Did you guys see these allegedly leaked slides from Luke Miani? What do we think?

View attachment 1792483
View attachment 1792484
If production is Q2, I don’t see how we can get a summer launch. However this is in contradiction with other rumours saying production had started in April. Wait & see I guess.

PS: EFI refers to the number of low power cores out of the core total (CPU). Don’t addition CPU and EFI.

If they start Q2 22 testing the 20 64 8 and the 40 128 8, would it be possible to buy a MacBook Pro 16-inch with these chips?
Q4 22
or Q1 23?

 

[cmaier]

If they start Q2 22 testing the 20 64 8 and the 40 128 8, would it be possible to buy a MacBook Pro 16-inch with these chips?
Q4 22
or Q1 23?

Typically takes 3 months to qualify chips, assuming no problems are found.

 

[leman]

If they start Q2 22 testing the 20 64 8 and the 40 128 8, would it be possible to buy a MacBook Pro 16-inch with these chips?
Q4 22
or Q1 23?

Never, because those are obviously desktop chips. A 20/64/8 is around 120 watts combined TDP, way too hot for a 16” chassis. Maybe on 2nm when the power consumption goes down by 50%…

 

[cmaier]

Never, because those are obviously desktop chips. A 20/64/8 is around 120 watts combined TDP, way too hot for a 16” chassis. Maybe on 2nm when the power consumption goes down by 50%…

They could always reduce clock/voltage.

Nah.