See I’m not a math guy, but assuming your formula is correct then you’ve answered my question (and then some). Thanks
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What microarchitecture choices have made M2 less efficient than M1?
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I've been looking but am unable to find how notebookcheck measures package power. Does anyone know?
EDIT: I found out from here https://www.notebookcheck.net/Our-Test-Criteria.15394.0.html They use a multimeter. So they are measuring at the wall instead of using powermetrics. That's disappointing.
EDIT: I found out from here https://www.notebookcheck.net/Our-Test-Criteria.15394.0.html They use a multimeter. So they are measuring at the wall instead of using powermetrics. That's disappointing.
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Untrue.
At any load below the thermal limits, the M2 is significantly faster than the M1. Even at it’s thermal limits, the M2 is still faster than the M1.
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That's outdated from 2016. Look at some of the more recent Macbook reviews where they specifically mention powermetrics.
https://www.notebookcheck.net/Apple...dia-Laptop-for-Content-Creators.579013.0.html
"The M1 Pro is also very efficient when we have a look at the internal consumption (via powermetrics) and there is no throttling or turbo peaks at the start of the benchmarks."
Untrue.
At any load below the thermal limits, the M2 is significantly faster than the M1. Even at it’s thermal limits, the M2 is still faster than the M1.
Untrue.
Is 19 not a bigger number than 18?Untrue.
I thought Apple's ARM SoCs were more efficient than Intel/AMD x86 CPUs because ARM SoCs take about the same time as x86 CPUs to finish the same task at lower frequency. Mx can do that because Apple has chosen to use wider/shorter pipelines, faster memory access, better branch predictors...
I wonder where cmaier is when you need him most.
Yes, and this is still true. M2 is still much more efficient than x86 CPUs for similar performance. .
That is still the case. However the way the youtubers measure efficiency does not tell you much about architectural efficiency. As I tried to explain, Cdyn (the so called switching capacitance) is the only architecture dependent parameter, which impacts efficiency , while V and f can be freely chosen from the frequency-voltage curve. In addition V is quadratic in the equation, so it has a big impact.
Mainly, x86 has to have an elaborate instruction stream parser that has to look at a bunch of bytes and figure out which ones go together to form each instruction; it then has to convert each instruction into its constituent μops to be fed into the pipe.
ARMv8+ does away with both of these issues: instructions are concise, so they very rarely require μops, since that is basically what they already are; and since all instructions are 32-bits long, the pipeline can just grab 16 bytes and already know it has 4 opodes there, just about ready to get stuffed right into the pipe as is.
In other words, x86 starts with a disadvantage.
He got banned, AAUI, for, reasons.
Offtopic, but made me wonder why Appel is using VLE for their custom GPU ISA. Of course, that's an in-order architecture, so probably decoding isn't a bottleneck in the first place and can be done efficiently, but code density matters a lot.
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I tried searching, but my searchfu isn't as stong as I'd like, what does VLA stand for?
I thought AMD used VLIW, but that appears to be a GCN/CDNA thing. Not 100% sure how RDNA2 would be classified.
EDIT: I found this by AMD, so it looks like VLIW hasn't been a thing for a few generations now.
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His side of the story is something like "I looked under the bridge and became angry that it had been allowed to reach such a state". If you were to ask, say, weaselbot, you would probably get a completely different narrative, about snowflakes and hurt fee-fees and how I should be reprimanded for even mentioning it.
I love math
Would you mind quoting the source of the formula that you’re using, and perhaps explain how it is accounting for architectural differences (e.g. path layout as oppoled switching capacitance in isolation) to account for fundamental differences such as M1 has no hardware accelerated logic for proRes, proRes Raw, or even the fundamental differences that anandtech identified between the newer blizzard efficiency cores which complete work faster and use a lower amount of energy go do so relative to anandtech.
I apologize if I have misunderstood your point on the formula - really I’m just looking for clarity as, in isolation, I do find myself questioning (not necessarily the formula itself which looks to determine efficiency as a measure of die size and capacitance) but the actual (relevance in isolation??) or applicability when comparing two fundamentally different pieces of silicon
Surely we cannot say that M1 decodes prores raw more efficiently at the same power envelope to M2 - so we should avoid hyperboles in the description and state scenarios where a situation holds true (or not)
Please can you help me understand better
.Many thanks,
Tom.
Wikipedia calls GCN "RISC SIMD".
More info about AMD's GPU:
An Overview of AMD’s GPU Architectures
Prefacing our deep-dive into TeraScale, GCN & RDNA…
An Architectural Deep-Dive into AMD’s TeraScale, GCN & RDNA GPU Architectures
With an overview of AMD’s GPUs and supporting prerequisite information behind us, it’s time to delve into TeraScale, GCN and RDNA’s…
I love math
Would you mind quoting the source of the formula that you’re using, and perhaps explain how it is accounting for architectural differences (e.g. path layout as oppoled switching capacitance in isolation) to account for fundamental differences such as M1 has no hardware accelerated logic for proRes, proRes Raw, or even the fundamental differences that anandtech identified between the newer blizzard efficiency cores which complete work faster and use a lower amount of energy go do so relative to anandtech.
I apologize if I have misunderstood your point on the formula - really I’m just looking for clarity as, in isolation, I do find myself questioning (not necessarily the formula itself which looks to determine efficiency as a measure of die size and capacitance) but the actual (relevance in isolation??) or applicability when comparing two fundamentally different pieces of silicon
Surely we cannot say that M1 decodes prores raw more efficiently at the same power envelope to M2 - so we should avoid hyperboles in the description and state scenarios where a situation holds true (or not)
Please can you help me understand better
Many thanks,
Tom.
The formula is just basic physics, you might find it in schoolbooks. You can also convince yourself that 1W = 1F * 1V^2 / s.
I am using it to demonstrate a common fallacy, which the OP fell for. Lets be more precise and define efficiency:
Efficiency = Performance/Power = (work/cycle)*f/Pdyn = (work/cycle*f)/(Cdyn*V^2*f) = (work/cycle)/Cdyn/V^2
As expected, since f is linear in power as well as in performance it cancels out. Still a higher voltage is required in order to reach higher frequencies.
When looking at the formula - only (work/cycle/Cdyn) is architecture dependent and constant per architecture. Otherwise efficiency is decreasing with the square of voltage for any architecture.
My point was that you cannot possibly conclude based on the presented data, which shows that the M2 is less efficient than the M1, that it has anything to do with architecture - my point was it has everything to do with voltage. And if you look at an iso-voltage scenario, you will see that the M2 is architectural more efficient than the M1 (e.g. work/cycle/Cdyn is higher for M2 compared to M1.)
Corollary, if you want to compare the efficiency of 2 different architectures - make sure you compare them at an iso-voltage point - and not at an iso-performance point (as many youtubers or people here in the forum would suggest).
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Say what? The trajectory of IC design has been the opposite of that. At higher frequencies, the cycle goes up to and across peak more smoothly when the difference between 0 and peak is less. '70s/'80s machines used +5 as peak, operating in the 001~300Mhz range; once we started getting close to the Ghz mark, voltages started to drop, in part because gating was being designed to respond properly at lower differentials. So, please stop blorting nonsense.
Uhm, your graph confirmed what the other posted stated.Untrue.
Although a bit old, "Computing's energy problem and what we can do about it" presentation is very instructive.
Summary of the presentation: https://www.gwern.net/docs/cs/hardware/2014-horowitz.pdf
Presenter wrote other interesting papers. For instance: "Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis".
Summary of the presentation: https://www.gwern.net/docs/cs/hardware/2014-horowitz.pdf
Presenter wrote other interesting papers. For instance: "Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis".
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