It sounds like you're saying it's more physically meaningful to choose a constant value for RC based on RC=1/(2f), rather than setting RC equal to 1/(2f). If so, and you use f=3 GHz, you get this, which is the expression you plotted:
Yep, that's what I meant. Assume the physical design is constant if you want to see how over and underclocking will impact power. Also, we don't know the physical process parameters (I'd imagine TSMC holds them very close to their collective chests), but the M-series is an existence proof of a 3GHz design that we can assume was well optimized, so it's a way of inferring the parameters from the evidence.
If I set Cdyn and Vgate to arbitrary constants to get the scaling behavior (as above, I used Cdyn = Vgate = 1), then I get approximately quadratic scaling between 1.5 GHz and 6 Ghz. The plot below compares the above equation (blue) to a power law with P ~ f^2.15 (dashed red):
Yeah, that lines up with "between square and cubed" if you're looking to avoid the extra math, and don't need to extrapolate too far from the where the fit was done. It looks like maybe 15-30% error on the low frequency end, a bit better on the high side? I'd guess another octave in either direction will look a bit worse. I can't imagine you'd ever raise the clock 4x from the design point though unless you're looking for YouTube views and some liquid nitrogen under the sink...
But, again, do you know what kind of power vs. frequency scaling we see in real processors?
It's hard to answer that with anything but "it depends" but this is a reasonable model for a digital circuit under modest clock rate changes. I haven't done a lot of experimentation myself with overclocking PC processors like this. I did some digging through overclocking threads to see what data I could find and, anecdotally, it looks like power increases a bit more than the square of the voltage, but then it gets murky what's CPU power versus other stuff on the board.
Remember, this all started by trying to understand a rule of thumb-- and yes that rule of thumb for a single transistor is a reasonable place to start from given how little we know about the process or the logic. The engineering team will be estimating power consumption with physical simulations that will include physics information about the process parameters from TSMC and logic information about toggle rates of the various transistors inside the design when operating.
P=fCV^2 is probably as close to right as we'll get without access to those simulations though. I think you might be looking for a more exact formula than you'll be able to find.
Oh, and since this is in a thread about differences between M1 and M2, the process parameters changed between N5 and N5P, so changing clock rates isn't the only variable in play.
You should pick up Mathematica
. That's what I've been using here. It also gives very precise control over numerical accuracy. Plus it's fun.
Yeah, I've seen people put it to really good use, and I've tried going to Mathematica several times, but I always get frustrated with it. It's not really a CAS, it's a programming language all its own and as nostalgic as the LISP-like symbolic processing is, I've always felt like I spent more time learning the system than solving problems. I keep bouncing between systems, but currently tend to favor Jupyter/Python and sympy. It doesn't have the sexy 3D plotting that Mathematica likes to show, but it's turned out I don't need that so much...
I tried Maple for a while too, and had the same experience.
If the capacitance is on the order of 10^-15 F, the resistance would be in the 10s of kOhms for RC to be on the order of 10^-10 s. Is the gate resistance really that high?
It's not the resistance of the gate, but the resistance to the gate that matters.
I'm really not familiar with the details of these bleeding edge processes, but as an order of magnitude, this doesn't seem crazy. I'm just spitballing the gate capacitance, as a start:
RC=1/6e9
C=10e-15
R=1e14/6e9=~17kΩ
R=r*L/A
Resistance is resistivity times length over cross section of the wire. Copper at 100C, the apparent operating temp of an M1, has a resistivity of about 2.2e-8 Ωm. It's hard to find estimates of interconnect width at 5nm, but something on the order of 10nm, so a cross sectional area of something like 1e-16.
L= RA/r = 17e3*1e-16/2.2e-8 = 75µm
So a 75µm wire into a 10fF capacitor has a time constant of 1/6e9. The M2 die is something like 12,000µm across, so the length doesn't seem crazy given that very few routes will be dead straight. This also ignores the source resistance of the driving stage and the resistance at the silicon interface.
Every transistor in the chip is different but the design has to accommodate the worst case timing path under worst case conditions.
