AMD Discussion

[AidenShaw]

The current tube is ok, the apu would took the GPU location with few revisions to the core, the few know about those HPC apu is it would tsp below 250W, with few nip tuck the core could handle 600W, also there is no challenge to run the APU interconnect fabric thru the former main board, my only concern is the dimm location as there is not much space behind the GPUs it should require so-dimm

Can you explain in more detail? Are there dual APUs? The GPU locations on the core (there are two of them) are narrow and very shallow. The CPU location is much wider and deeper.

Are you suggesting that the new core should be an equilateral triangle, instead of a right triangle?

It would be quite a stretch to call a system using SO-DIMMs a "workstation".

You're describing a system that's approaching 800 watts for power consumption - I think that you'd need a significantly larger cylinder for that.

 

[Mago]

Are there dual APUs?

http://vrworld.com/2016/02/12/cern-confirms-amd-zen-high-end-specifications/

ZEN High End Exascale APU, 1-2 Socket (1P-2P) – rumored specs from Fast Forward

16 ZEN x86 Core, 6-wide
64 KB L0 Cache (4KB per core)
1 MB L1 D-Cache (64KB per core)
1 MB L1 I-Cache (64 KB per core)
8 MB L2 Cache (512 KB per core)
8 MB L3 Cache (512 KB per core)
288-bit CPU Memory Controller (4×72-bit, 64-bit + 8-bit ECC)
102.4 GB/s via DDR4-3200 (ECC Off)
85.3 GB/s via DDR4-2666 (ECC On)
102.4 GB/s between CPU and GPU via GMI
~2000-core Polaris GPU
2048-bit GPU Memory Controller
4 GB HBM SGRAM Memory (2 chips at 2GB)
512 GB/s GPU Bandwidth

TL;DR:
Exascale Zen Apu to share socket with Server Zen (Not AM4/AM4+) 2TFlop FP64/APU, not the same APU as consumer Zen APU (it will be a 4 core unit, I mean)
.

 

[AidenShaw]

http://vrworld.com/2016/02/12/cern-confirms-amd-zen-high-end-specifications/

The CERN leak about multi-socket Zens has nothing to do with any possible MP6,1 follow-on.

How will you possibly fit dual APUs and RAM and 800 watts of stuff into a form factor that seems to regularly burn up with its 450 watt power supply?

The E5-26xx v2 CPUs used in the old tube were capable of multi-socket operation. Did Apple ever make a dual socket system with the MP6,1 - no.

Very possible with a larger tube - but not the 2013 model. That was the crux of my comment - it would be possible with a redesigned tube, but the 2013 tube can barely deal with its current components.

 

[koyoot]

For those who eagerly wait for any information about Zen:

http://events.linuxfoundation.org/s...6 Memory Encryption Technology LSS Slides.pdf

The interesting bit is Security subsystem in the CPU.

 

[koyoot]

http://fudzilla.com/news/processors/41678-amds-7nm-apu-is-gray-hawk

Very far future plans for AMD, according to FUDZilla. They are clueless however to the degree that they believe that Zen APUs will use Polaris architecture and the GPU.

They won't.

http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver

SI: TAHITI
CI / GFX7: MILOS, KRYPTOS, HAWAII, NEVIS, PENNAR, BONAIRE, Kabini
VI / GFX8: ICELAND, TONGA, CARRIZO, BERMUDA, racerx, FIJI
GFX81: AMUR, STONEY, ELLESMERE, DERECHO
GFX9: GREENLAND, RAVEN1X, VEGA10, VEGA11

Vega is the same GPU family as Greenland and... Raven Ridge APU family. Raven Ridge is the codename for 14/16 nm Zen APUs.

 

[Stacc]

Very far future plans for AMD, according to FUDZilla. They are clueless however to the degree that they believe that Zen APUs will use Polaris architecture and the GPU.

Why is this wrong? If AMD wants to put out an APU for a MacBook pro type notebook with a TDP of ~45-65 W, then any of the bigger Vega parts won't fit. It seems like Polaris 11 would be a good fit here. As far as I know by middle of next year there won't be any other AMD GPUs in this envelope.

 

[koyoot]

Why is this wrong? If AMD wants to put out an APU for a MacBook pro type notebook with a TDP of ~45-65 W, then any of the bigger Vega parts won't fit. It seems like Polaris 11 would be a good fit here. As far as I know by middle of next year there won't be any other AMD GPUs in this envelope.

Read again, what is OpenCL drivers. Raven Ridge APU/Zen APUs are the same family as Greenland and Vega GPUs. Stoney Ridge is the same technology as Polaris(fact), and it is the same GPU family.

Whats more, Zen APUs have 2048 bit memory controller for 2 stacks of HBM2.

 

[Stacc]

Read again, what is OpenCL drivers. Raven Ridge APU/Zen APUs are the same family as Greenland and Vega GPUs. Stoney Ridge is the same technology as Polaris(fact), and it is the same GPU family.

Whats more, Zen APUs have 2048 bit memory controller for 2 stacks of HBM2.

Ah, I think I get it. I don't think I'll ever be able to keep AMD's code names straight. Any GPU that appears on an APU is not the same chip that appears in a discrete card. That wasn't clear to me before. Its too bad they can't just drop in any GPU. This would give many more options for configuring these CPU+GPU combinations.

 

[ManuelGomes]

Don't think it will happen, not this time around at least, but:

http://wccftech.com/apple-macbook-pro-amd-zen/

 

[koyoot]

http://www.bitsandchips.it/52-english-news/7478-apu-zen-in-macbook-pro-between-2017-and-2018

This is the original source. Speculation article, nothing more, nothing less, however...

Intel is focusing on delivering external expansion(eGPUs) to counter Zen APUs, because... they are simply not able to design and bring GPUs to competitive levels.

Imagine that for Example Zen can be as fast as Haswell, have 2 GB of HBM2 shared between CPU and GPU, and offer 1536 GCN cores in the die. That is what Intel has to deal with, and be competitive at pricing.

What is funnier, very large number of computers are 5 years old, even Apple advertised their iPad Pro as a replacement for them. What do you think what people will do, when they will face choice, of buying new CPU and GPU, or single unit, for less?

 

[cube]

It is ridiculous to suggest an iPad can replace my 2011 17" cMBP.

Even an rMBP can't.

That's why I am trying to get my eGPU to work properly for 3D in Sierra (Windows 10 PC is OK).

 

[Joe The Dragon]

eGPU is still limited by TB pci-e 3.0 X4.

And if amd zen can do 32 pci-e lanes per cpu or even 16+4 with usb / sata / pci-e storage / network / etc having then own lanes not part of the 16+4 then Intel is in deep.

 

[koyoot]

It is ridiculous to suggest an iPad can replace my 2011 17" cMBP.

Even an rMBP can't.

That's why I am trying to get my eGPU to work properly for 3D in Sierra (Windows 10 PC is OK).

In terms of performance or screen estate? Currently iPad Pro can be on par with your MBP17 in terms of performance.

 

[cube]

In terms of performance or screen estate? Currently iPad Pro can be on par with your MBP17 in terms of performance.

In terms of functionality.

 

[koyoot]

In terms of functionality.

I get it .

 

[Mago]

the original source. Speculation article, nothing more, nothing less

Sometimes I believe those who writes these speculative articles, just come to forums for trending speculations then they compile it add some own speculations then publish, later we read these "original" article (actually our own speculations recycled) and we comeback with links to these pages happy to see our speculations as "leaks" or backed by someone... (moreless the same I did with DarkNetGuy I admit)

 

[koyoot]

Well Bits&Chips was announcing in December last year that AMD delivered Engineering samples of Zen CPUs to Apple. Thats why they cane out with this information. Also SemiAccurate few years ago was saying that in few years Intel will go out of Apple hardware, and that its a done deal, so...

Don't get me wrong. Bits&Chips is very well informed. They have very good sources, but that article is not even having any substantial information in it, only speculation about the possibility.

 

[ManuelGomes]

http://wccftech.com/amd-zen-32-core-naples-cpu-benchmarks-leaked/
Now that would fit nicely in the nMP...
ES being tested, availability only in Q2'17.
Maybe Apple has been testing it?!

 

[ManuelGomes]

Zen brings new encryption:
http://wccftech.com/amd-zen-encryption-sme-sev-hw-based-sha/

 

[cube]

This feature seems quite on par with the introduction of AMD64.

 

[ManuelGomes]

And Intel is again following lead...

 

[tuxon86]

And Intel is again following lead...

The Intel Core serie has had encryption features since 2010...

https://software.intel.com/en-us/articles/intel-advanced-encryption-standard-instructions-aes-ni

 

[cube]

The Intel Core serie has had encryption features since 2010...

https://software.intel.com/en-us/articles/intel-advanced-encryption-standard-instructions-aes-ni

We are not talking about encryption instructions, but about encrypted RAM.

 

[tuxon86]

We are not talking about encryption instructions, but about encrypted RAM.

Which Intel aslo have under another name.

 

[AidenShaw]

Which Intel aslo have under another name.

https://software.intel.com/en-us/sgx

https://software.intel.com/en-us/bl...cryption-an-intel-sgx-underpinning-technology

Abstract: Cryptographic protection of memory is an essential ingredient for any technology that allows a closed computing system to run software in a trustworthy manner and handle secrets, while its external memory is susceptible to eavesdropping and tampering.

An example for such a technology is Intel's emerging Software Guard Extensions technology (Intel SGX) that appears in the latest processor generation, Architecture Codename Skylake. This technology operates under the assumption that the security perimeter includes only the internals of the CPU package, and in particular, leaves the DRAM untrusted.

It is supported by an autonomous hardware unit called the Memory Encryption Engine (MEE), whose role is to protect the confidentiality, integrity, and freshness of the CPU-DRAM traffic over some memory range. To succeed in adding this unit to the micro architecture of a general purpose processor product, it must be designed under very strict engineering constraints. This requires a careful combination of cryptographic primitives operating over a customized integrity tree that mostly resides on the DRAM while relying only on a small internally stored root.

The purpose of this paper is to explain how this hardware component of SGX works, and the rationale behind some of its design choices. To this end, we formalize the MEE threat model and security objectives, describe the MEE design, cryptographic properties, security margins, and report some concrete performance results.

The whitepaper can be found here.​