Is the new Mac Pro a failure?

[Mago]

I didn't realize the Skylake Xeon's with 48 lane PCIE weren't shipping until 2017. This leaves TB3 as very doubtful in my mind for the MacPro 7,1.

As you say, the only CPU's Apple is left with are the 1600 and the 2600 Broadwell-ep with 40 lanes and that still uses the C610 chipset with 8 PCIE 2.0 Lanes, so in order to get Thunderbolt 3 they need to come up with 8 more PCIE lanes.

1. Intel could build Apple a custom chipset with 16 PCIE lanes
2. Apple could cut the link speed of the second GFX card to 8x
3. Apple could use 2 1600 CPU's and only offer TB3 on the high end MP7,1

1 is the best case, 2 is the wisest move, the second GFX card doesn't do anything most of the time and we're still talking about and 8x link at PCIE 3.0 speeds. 3, I'm not even sure if the 1600 supports SMP or Apple could even fit 2 of them in the nMP case even if they did.

None of the above are very likely, what is likely is we'll see a refresh of the MacPro at WWDC 2016 in June /without TB3.

Xeon E5v4 are confirmed to be available on March/April.

Tb3 also is confirmed by leaks on OSX beta,

Tb3 runs on Pcie 3 (2/4 lines) "in a tipical implementation wired to the cpu root complex not the PCH" tipical here means not the unique way to wire it.

https://thunderbolttechnology.net/

It's more likely a custom c610 to be released for tb3 but not the only choice.

Haswell-EP on C610 leaves 40pcie 3 lines, from those Apple could take 4 pcie 3 lines for 2 tb3 headers and have 4 available for 1/2x NVMe, or take all 8 for 4 tb3 headers.

I'm speculating, I think at some point Intel should announce either a custom x99/c610 "tuned" for tb3.

At the moment osx beta leaks, point to 4 tb3 ports (2 headers), and 6 tb2 ports or usb3 (using the PCH).

 

[Mago]

Another solution to explain that leak on OSX is Apple to switch to Xeon E3 for the Mac Pro, this is consistent with Intel purpose to segregation among severs and workstations, let's see I don't know enough on Skylake Xeon E3 but I think only foresee 4 cores.

 

[DearthnVader]

Xeon E5v4 are confirmed to be available on March/April.

Tb3 also is confirmed by leaks on OSX beta,

Tb3 runs on Pcie 3 (2/4 lines) "in a tipical implementation wired to the cpu root complex not the PCH" tipical here means not the unique way to wire it.

https://thunderbolttechnology.net/

It's more likely a custom c610 to be released for tb3 but not the only choice.

Haswell-EP on C610 leaves 40pcie 3 lines, from those Apple could take 4 pcie 3 lines for 2 tb3 headers and have 4 available for 1/2x NVMe, or take all 8 for 4 tb3 headers.

I'm speculating, I think at some point Intel should announce either a custom x99/c610 "tuned" for tb3.

At the moment osx beta leaks, point to 4 tb3 ports (2 headers), and 6 tb2 ports or usb3 (using the PCH).

Haswell-EP offers 40 PCIE 3.0 lanes from the CPU and 8 PCIE 2.0 lanes from the C610 PCH, just like the MacPro6,1 with the C600 PCH.

A custom X99 would be nice, but I don't know if Intel would be willing to do it, on the PC side they can just offer one PCIE 16x 3.0 slot on an X99 MB with TB3 and one 8x slot and free up enough bandwidth for three TB3 ports.

A custom chip would only be a stop gap util Skylake Xeon with 48 lanes ship anyway.

 

[Stacc]

Another solution to explain that leak on OSX is Apple to switch to Xeon E3 for the Mac Pro, this is consistent with Intel purpose to segregation among severs and workstations, let's see I don't know enough on Skylake Xeon E3 but I think only foresee 4 cores.

This may work for the low end version of the mac pro but will not be a substitute for the 6+ core versions. Xeon E3s also are limited in how many PCIe lanes they have so they would not be good with a dual video card configuration.

My bet is Apple keeps the same configuration as the current mac pro. A PCIe switch will be used to distribute bandwidth between the 3 thunderbolt 3 controllers. Of course, each controller is not guaranteed its full bandwidth depending on the load of the other controllers but the maximum bandwidth available to a single controller is higher. I don't think there are too many use cases in which all 3 thunderbolt controllers would be saturated at the same time. Also, I don't think displayport over thunderbolt counts against the PCIe bandwidth.

 

[DearthnVader]

Also, I don't think displayport over thunderbolt counts against the PCIe bandwidth.

Good point, one would assume when you connect a TB display, HDMI, or DP, your no using the bandwidth of the PEX 8723 but the bandwidth of the GFX card. We assume that anyway.

 

[Mago]

This may work for the low end version of the mac pro but will not be a substitute for the 6+ core versions. Xeon E3s also are limited in how many PCIe lanes they have so they would not be good with a dual video card configuration.

My bet is Apple keeps the same configuration as the current mac pro. A PCIe switch will be used to distribute bandwidth between the 3 thunderbolt 3 controllers. Of course, each controller is not guaranteed its full bandwidth depending on the load of the other controllers but the maximum bandwidth available to a single controller is higher. I don't think there are too many use cases in which all 3 thunderbolt controllers would be saturated at the same time. Also, I don't think displayport over thunderbolt counts against the PCIe bandwidth.

In a "non-tipical" tb3 implementation, w/o bridges using only the pcie lanes as just another pcie peripheral, the leaked configuration has sense this way:

Leak 4tb3/usb-c ports : two headers tb3 shared by 4 ports using only 4 pcie 3 lanes.
Leak 6tb2/usb3: c610 PCH provides 8 pcie lines enough for 2 tb2 controllers and 6 usb3

Still having 4 pcie 3 for 1 or 2 NVMe blades. (I fear only 1).

Memory ddr4 2400 ecc.

Video, something based on Fiji as AMD has no Leaked nothing on the Dx00 replacements, hopefully to include ECC VRAM (but unlikely considering Cuppertino's vacuum salesman minded management)

 

[tuxon86]

Apple could use a second CPU instead of using a second GPU which pretty much no one uses anyway and drive every component with the maximum PCIe Lanes. But it's the 2016 Prosumer Apple, so won't ever happen.

The CPU board is bigger than the GPU one. The would have to redesign the case.

 

[Mago]

Maybe the nnMP to have only 6 usb3 + 4 tb3/usb-c and 4 tb2 (instead 6 as was speculated), since the leak is related to usb-c/usb3 configuration only, this falls on the c610 reach, no bridges required.

 

[ManuelGomes]

Intel won't custom the C610 just for Apple, I very much doubt that.
We'll see 2 TB3 controllers (4 ports) on the CPU, 6 USB ports off the PCH and the SSD will remain on the PCH as well - still PCIe2 though, unfortunately.
I believe that's the wisest option available at the moment.
[doublepost=1452101837][/doublepost]Mago, the PCH has 8 lanes but they can't all be used by the TB2 controllers, you need 4 for the SSD and 3 for the GbE and WiFi/BT.

 

[DearthnVader]

Intel won't custom the C610 just for Apple, I very much doubt that.
We'll see 2 TB3 controllers (4 ports) on the CPU, 6 USB ports off the PCH and the SSD will remain on the PCH as well - still PCIe2 though, unfortunately.
I believe that's the wisest option available at the moment.

There is only bandwidth for 1.5 TB3 ports, that's the whole point I'm trying to make.

Apple is using all 48 lanes.

C600 PCH( 8 PCIE 2.0 )
1x lane GigE Controller
1x lane the other GigE controller
1x lane 802.11ac controller
1x lane USB3 controller
4x lanes PCIE SSD controller

CPU ( 40 PCIE 3.0 )
16x AMD Dxxx
16x the other AMD Dxxx
8x PEX 8723 TB2 Hub

 

[Mago]

Intel won't custom the C610 just for Apple, I very much doubt that.
We'll see 2 TB3 controllers (4 ports) on the CPU, 6 USB ports off the PCH and the SSD will remain on the PCH as well - still PCIe2 though, unfortunately.
I believe that's the wisest option available at the moment.

I'll account only a single tb3 controller (4 pcie 3 lanes) driving 4 ports (as the tb2 ports on the nMP have only 3 (or 2?) controllers driving 6 tb2 ports).


Edit: leaving available 4 pcie 3 lines is mandatory in case Apple want to include an NVMe, it's enough known El Capitan Included NVMe drivers

 

[DearthnVader]

I'll account only a single tb3 controller (4 pcie 3 lanes) driving 4 ports (as the tb2 ports on the nMP have only 3 (or 2?) controllers driving 6 tb2 ports).


Edit: leaving available 4 pcie 3 lines is mandatory in case Apple want to include an NVMe, it's enough known El Capitan Included NVMe drivers

The MacPro 6,1 has 6 TB2 ports sharing the bandwidth of 8x PCIE 3.0 7.8GB/s. Each set of two TB ports( one HDMI/TB ) gets 2.5 GB/s.

 

[Mago]

The MacPro 6,1 has 6 TB2 ports sharing the bandwidth of 8x PCIE 3.0 7.8GB/s. Each set of two TB ports( one HDMI/TB ) gets 2.5 GB/s.

The Ivi-Bridge-E nMacPro uses C602J chipset, having 8 PCIe 2 lines available, according http://www.anandtech.com/show/7049/intel-thunderbolt-2-everything-you-need-to-know each Tb2 heades is feed by 4 Pcie 2 lines from PCH.

if not rigth, please provide some link supporting TB2 on nmp is feed by Pcie3 lines.
[doublepost=1452107914][/doublepost]

Good point, one would assume when you connect a TB display, HDMI, or DP, your no using the bandwidth of the PEX 8723 but the bandwidth of the GFX card. We assume that anyway.

Graphics connect to the TB2 header by its own bus, do not share PCIe2 bus bandwidth, only when a TB peripheral shares the connector (and cable) with an DP display is when the cable shares its bandwidth or lines more specifically.

 

[AidenShaw]

The Ivi-Bridge-E nMacPro uses C602J chipset, having 8 PCIe 2 lines available, according http://www.anandtech.com/show/7049/intel-thunderbolt-2-everything-you-need-to-know each Tb2 heades is feed by 4 Pcie 2 lines from PCH.

if not rigth, please provide some link supporting TB2 on nmp is feed by Pcie3 lines.
[doublepost=1452107914][/doublepost]
Graphics connect to the TB2 header by its own bus, do not share PCIe2 bus bandwidth, only when a TB peripheral shares the connector (and cable) with an DP display is when the cable shares its bandwidth or lines more specifically.

Note the PCIe switch in the center - it expands 8 PCIe 3.0 lanes to 16 PCIe 2.0 lanes. 4 lanes for each T-Bolt2 controller, 1 lane for USB 3.0, and 3 lanes unused.


This diagram has been posted here many times, e.g. https://forums.macrumors.com/thread...pu-driver-issues.1860297/page-3#post-21167415 .

 

[ManuelGomes]

OS X 10.11.3 beta 2 brings anything new?

 

[AidenShaw]

There is only bandwidth for 1.5 TB3 ports, that's the whole point I'm trying to make.

Apple is using all 48 lanes.

C600 PCH( 8 PCIE 2.0 )
1x lane GigE Controller
1x lane the other GigE controller
1x lane 802.11ac controller
1x lane USB3 controller
4x lanes PCIE SSD controller

CPU ( 40 PCIE 3.0 )
16x AMD Dxxx
16x the other AMD Dxxx
8x PEX 8723 TB2 Hub

Almost correct - see https://forums.macrumors.com/threads/is-the-new-mac-pro-a-failure.1939541/page-55#post-22438186

C600 PCH ( 8 PCIe 2.0 )

4x lanes PCIe SSD controller
1x lane GigE Controller
1x lane the other GigE controller
1x lane 802.11ac controller (at PCIe 1 speed)
1x lane unused​

CPU ( 40 PCIe 3.0 )

16x GPU A (compute)
16x GPU B (render/displays)
8x PEX 8723 PCIe to PCIe switch (configured for 8 PCIe 3.0 lanes to 16 PCIe 2.0 lanes)

4x lanes TB controller A
4x lanes TB controller B
4x lanes TB controller C
1x lanes USB 3.0
3x lanes unused​

 

[Mago]

Note the PCIe switch in the center - it expands 8 PCIe 3.0 lanes to 16 PCIe 2.0 lanes. 4 lanes for each T-Bolt2 controller, 1 lane for USB 3.0, and 3 lanes unused.
View attachment 609164

This diagram has been posted here many times, e.g. https://forums.macrumors.com/thread...pu-driver-issues.1860297/page-3#post-21167415 .

Ok, interesting, few things to consider, C602 dont includes native USB3, this maybe the reason why Apple choose to use an PCIe switch to plug the USB3 and the Thunderbolt 2, C610 includes USB3, as Alpine Ridge includes USB-C. un the current nMP apple connected the SSD thru PCIe 2 this can not be made with NVMe SSD which requires 2 or 4 PCIe 3 lines, so it's possible to re-organize the buses as I mentioned:

[Xeon E5v4]=== 32x PCIe 3 Lines === [GPU 1 & 2]
| || ||
| || ||=== 4x PCIe 3 Lines === [Alpine Ridge]==[ 2x Tb3 + 2xUsb-C + 2x 10GbE] x2
| ||
| ||
| || ===== 4x PCIe 3 Lines === [NVMe]
|
¦
DMI 2.0
|
|
[C610 PCH]==== 8x PCIe 2 === [Falcon Ridge] ==[2x Tb2] x2
|||
|||
[6x USB3.0 + Audio+ 2xGbE+ Other I/O]

Leaked info on OSX El Capitan Beta, pointout 4 USB-C 3.1 and 6 USB 3 , no cues on TB2 arrangements, we known that USB-C is tied to TB3, so each TB2 header providing for 2 USB-C ports for 4 total USB-C/TB3, as with current nMP only one TB port at each controller can operate at FULL speed at time. the 4x TB2 ports are my speculation.

https://pikeralpha.wordpress.com/2015/11/01/first-signs-of-new-macpro71-found-in-el-capitan/

https://www.macrumors.com/2015/11/0...8b021f2-63d6-4a8c-9d9f-5a7a87d1606c&CFTOKEN=0

Which account 4x HS (high speed) USB port and 6x SS (std speed) USB ports.

 

[MacVidCards]

Who told you NVMe required PCIE 3?

Works fine in my cMP in PCIE 2.

In fact it is faster than when I plug it into my nMP where the TB2 overhead/latency drags speed down.

 

[AidenShaw]

Ok, interesting, few things to consider, C602 dont includes native USB3, this maybe the reason why Apple choose to use an PCIe switch to plug the USB3 and the Thunderbolt 2, C610 includes USB3, as Alpine Ridge includes USB-C. un the current nMP apple connected the SSD thru PCIe 2 this can not be made with NVMe SSD which requires 2 or 4 PCIe 3 lines, so it's possible to re-organize the buses as I mentioned:

[Xeon E5v4]=== 32x PCIe 3 Lines === [GPU 1 & 2]
| || ||
| || ||=== 4x PCIe 3 Lines === [Alpine Ridge]==[ 2x Tb3 + 2xUsb-C + 2x 10GbE] x2
| ||
| || ===== 4x PCIe 3 Lines === [NVMe]
|
DMI 2.0
|
[C610 PCH]==== 8x PCIe 2 === [Falcon Ridge] ==[2x Tb2] x2
|||
|||
[6x USB3.0 + Audio+ 2xGbE+ Other I/O]

Leaked info on OSX El Capitan Beta, pointout 4 USB-C 3.1 and 6 USB 3 , no cues on TB2 arrangements, we known that USB-C is tied to TB3, so each TB2 header providing for 2 USB-C ports for 4 total USB-C/TB3, as with current nMP only one TB port at each controller can operate at FULL speed at time. the 4x TB2 ports are my speculation.

https://pikeralpha.wordpress.com/2015/11/01/first-signs-of-new-macpro71-found-in-el-capitan/

https://www.macrumors.com/2015/11/0...8b021f2-63d6-4a8c-9d9f-5a7a87d1606c&CFTOKEN=0

Which account 4x HS (high speed) USB port and 6x SS (std speed) USB ports.

I'm having trouble figuring out what you mean with all of the pipes and equals.... Maybe if you'd format it as a nested list (like I did) it would work for me.

 

[Mago]

Who told you NVMe required PCIE 3?

Works fine in my cMP in PCIE 2.

In fact it is faster than when I plug it into my nMP where the TB2 overhead/latency drags speed down.

NVMe on M.2 blades connects to PCIE-3

 

[Mago]

I'm having trouble figuring out what you mean with all of the pipes and equals.... Maybe if you'd format it as a nested list (like I did) it would work for me.

Sorry, I originally edited on my desktop, on tapatalk the whitespaces are removed.

 

[Stacc]

Note the PCIe switch in the center - it expands 8 PCIe 3.0 lanes to 16 PCIe 2.0 lanes. 4 lanes for each T-Bolt2 controller, 1 lane for USB 3.0, and 3 lanes unused.
View attachment 609164

This diagram has been posted here many times, e.g. https://forums.macrumors.com/thread...pu-driver-issues.1860297/page-3#post-21167415 .

It looks like the SSD shares bandwidth with one of the GPUs. There is no reason they couldn't do this again.

 

[MacVidCards]

NVMe on M.2 blades connects to PCIE-3

Also connects to PCIE 2.0, as I mentioned. Doesn't require PCIE 3

 

[DearthnVader]

The Ivi-Bridge-E nMacPro uses C602J chipset, having 8 PCIe 2 lines available, according http://www.anandtech.com/show/7049/intel-thunderbolt-2-everything-you-need-to-know each Tb2 heades is feed by 4 Pcie 2 lines from PCH.

if not rigth, please provide some link supporting TB2 on nmp is feed by Pcie3 lines.

http://www.anandtech.com/show/7603/mac-pro-review-late-2013/8

 

[Mago]

Also connects to PCIE 2.0, as I mentioned. Doesn't require PCIE 3

Where will go faster?

Assuming you're right:

In case Apple decides to go 1:1 o tb3 header to ports, this case they will need the remaining 8 pcie 3 lines for 2 Alpine Ridge, the SSD would be using 4x pcie 2 lines from PCH and 2 legacy tb2 using the last 4 pcie 2 lines...

It's an possibility ( 4 tb3 + 2 tb2 + NVMe on Pcie 2) and still fit between the leaked information.