NVMe with ST-NGFF2013-C; Vega Internal GPU; Mac Pro 2013 (6,1)

[CodeJingle]

In theory, MLC is more reliable and has a longer life than TLC (10000 cycles vs 5000).

The specs for both drives are claiming MTBF of 1,500,000 hours though. The time should be cut in half if the cycle count is 50%. Maybe a documentation error?

... looks like the cache on the 970 evo is double compared to 960 pro (2gb vs 1gb). so empirically on average the evo is faster with double the cache but worst case on edge cases maybe the 960 pro is faster.

well the mystery is solved*.

(*: not really)

specs for 970 evo


specs for 960 pro

 

[Kris Kelvin]

The specs for both drives are claiming MTBF of 1,500,000 hours though.

That's basically just saying that if you have 1000 of these drives running (powered), every 60 days one of them will fail (on average). It's unrelated to the amount of data read/written, which might* still exhaust program/erase cycles much sooner.

* actual flash endurance may be better than specified, as shown in this test

 

[CodeJingle]

That's basically just saying that if you have 1000 of these drives running (powered), every 60 days one of them will fail (on average).

Oh wait nevermind, on Samsung's own site they say 970 EVO is using 'MLC' and the same advanced heat spreading crap as the 960 PRO. So the 970 EVO still seems better than 960 PRO, and with double the cache, and 33% cheaper, and overall the same useful lifetime. My hard drive is sooo outdated lol.

... yeah you are at least half right in that the PRO is using 2-bit memory and the EVO 3-bit but Samsung claims them both as 'MLC'

... theoretically when 970 PRO comes out with a 2TB model it will have the same 2GB of cache. so the only other difference between 970 EVO 2TB and 970 PRO 1TB appears to be that write speed is 4 to 10% faster on the 970 PRO (all read speeds are the same). though there may be further improvement when 970 PRO 2TB comes out. i am hoping they eventually also release a single stick 4TB NVMe drive.

http://www.samsung.com/semiconductor/minisite/ssd/product/consumer/970evo

http://www.samsung.com/semiconductor/minisite/ssd/product/consumer/970pro

quoted from the EVO site:

• STORAGE MEMORY
  Samsung V-NAND 3-bit MLC

"Samsung’s advanced nickel-coated controller and heat spreader on the 970 EVO enable superior heat dissipation. The Dynamic Thermal Guard automatically monitors and maintains optimal operating temperatures to minimize performance drops."

 

[CodeJingle]

Some more delayering. I think I went overboard for spring cleaning. I've thrown out half my furniture. I even threw out one of the closet doors (when you open your closet all the way the surface area covered by the doors should not be more than half).

 

[MarkJames68]

i had thought there was a warranty difference but I guess not. Interesting.

 

[CodeJingle]

i had thought there was a warranty difference but I guess not. Interesting.

the offered warranty may have changed. or someone went back in time and changed that one tiny thing just to mess with you, but you still somehow remember the original timeline.

 

[sbarton]

The adapter is passive it should have no effect on internal vs external. The drive should be showing up as internal. Though I can't double check at the moment, if anyone else wants to chime in here.

The PM961 I have shows up as internal once booted into the OS. It only shows as external in startup manager.

 

[CodeJingle]

logic board by the pool

 

[CodeJingle]

experimental way to clean a circuit board ... maybe it works i'm not sure ... at least my process is certainly awkward to talk about ... but use anhydrous isopropyl alcohol at 99.9% not 70%

https://www.dropbox.com/s/vc2stt9a055me3h/20180521_184721.mp4?dl=0

https://www.amazon.com/dp/B0797BZDM5

 

[CodeJingle]

I noticed the asymmetric shape of the flex cable connector. All three connectors are oriented in the same direction based on this asymmetry so I should revise my previous statement about the matching ordering to use for pin ids.

Update: Yeah I went back and updated the previous reference I had made for the orientation of the three flex cable connectors. I was only wrong for the IO board flex cable connector orientation. But I still need to update the numbers documents.

 

[CodeJingle]

female and male connectors for graphics flex cable (female connector based on feedback from dwdrummer959)

female
https://www.digikey.com/product-detail/en/amphenol-fci/84501-101LF/609-1097-1-ND/1002969

male
https://www.digikey.com/product-detail/en/amphenol-fci/84500-102LF/609-1095-1-ND/1002968

 

[Selsk]

Some guy from the Mac Pro research division just spit up his coffee. "OH GOD NO HE FOUND THE CONNECTORS"

 

[CodeJingle]

these are the 320 pin io board flex cable connectors, but they are non-stock with an 8 week lead time, and lol the minimum quantity is 250 units. maybe they can be found in stock elsewhere in small quantity like mouser or ebay (i may check later).

female
https://www.digikey.com/product-detail/en/amphenol-fci/10123982-101LF/10123982-101LF-ND/5208353

male
https://www.digikey.com/product-detail/en/amphenol-fci/10123981-102LF/10123981-102LF-ND/5208346
[doublepost=1527025146][/doublepost]two 300 pin female connectors plugged into the logic board. seems to fit though i haven't checked continuity

 

[CodeJingle]

Putting together trinocular double-boom stereo microscope. This was a personal purchase. It can help with the Mac Pro R&D stuff but it was mostly for quality of life in my day job.

AmScope is kind of low to midrange but at least in its class I got the best model they make for electrical rework, ZM-4TNW3 (without illumination or digital cameras which can both be purchased separately).

update: can adjust distance between the eyes easily (after a few tries to figure it out).

http://www.amscope.com/2x-225x-trinocular-boom-stereo-microscope-w-focusable-eyepieces.html

https://www.dropbox.com/s/nieo2qseovz9a8x/DAW Series Manual Complete.pdf?dl=0

https://www.dropbox.com/s/fejuwa9vrvg34bx/ZM Series Manual Complete.pdf?dl=0

 

[MIKX]

You must have a very patient and understanding wife . . . . . or you are recently divorced
That said, you certainly are a valuable repository of arcane Apple secrets.
I applaud your tenacity and attention to detail.

 

[CodeJingle]

You must have a very patient and understanding wife . . . . . or you are recently divorced

'Long time ago divorced.' You have little to fear unless my kids move out or the startup I work at starts sustaining profit.

 

[CodeJingle]

After a short break I've started on the 2nd spare logic board. It took two hours to remove one connector without destroying the underlying trace that is the tedious nature of this work. My previous delayering of the logic board I literally ripped the connector off. The build quality of this connector is outstanding or according to Viticci's scale 'Best, I Love You.'

 

[CodeJingle]

Still a flew missing traces but overall much better than the previous run with the logic board. other layers should be similarly improved. Also I noticed comparing the logic board vs the cpu riser card, layers on the logic board are much thinner.

The thickness of the copper in each layer is also thinner compared to the cpu riser card. boring through this board is more fun.

I got through to the third layer of the front of the board which is the second signal plane. This is an excellent scan of the layer. Even in the crusty spots from overheating without enough flux you can still see the traces. Minimal trace loss here.

The only glaring issue of this board is that the planes closest to the center are pure signal planes and are sandwiched together directly adjacent. Especially with pure signal planes you need a ground plane between them. Worst case, you need to merge a ground plane into both signal planes using copper pour (if you want directly adjacent signal traces). The thickness of the resin in the middle between the two halves is minimal, so that isn't a factor. Every other adjacent pair of layers seem to follow the rules.

Ideally, every layer is either 1) solid ground plane with signal and power passing straight through with VIAs no traces for signal/power, or 2) full copper pour, and everywhere that isn't signal or power is ground. You get cleaner signals and cleaner power that way. Unless I am missing something here (I'm still a noob when it comes to electrical engineering).

update: i rescanned the front and back second signal layer while the board was submerged in anhydrous isopropyl alcohol (99.9%) inside of a ziploc bag. this surfaces the traces better since the copper isn't quite exposed (i left a faint layer of resin to protect the traces from falling off the board) and also seems to work better for the crusty parts.

update: all signal layers of second spare logic board are bored into and scanned. note the deepest two signal layers are intermingling with no ground plane between them which might be a problem.

front




back

 

[CodeJingle]

hit a new milestone today. i have all the traces for all the pcie lanes documented, all the way from the cpu socket pins on the cpu riser card to the pins of the two graphics flex cable connectors on the logic board. from sea level and deeper the first and second signal layers on the cpu riser card, including front and back (so four signal layers total) account for all the pcie lanes of the cpu. preview shots of those four layers below.

the cpu riser card traces are unbroken so i don't need to go back and do it again later. i do need to do it again for the logic board, which i finished. so this milestone is more or less 100% official.

now there is some work i need to do in post, including further progress on the spreadsheets, and physically following all the lines so to speak to double check and confirm everything. so stuff isn't labeled yet.

still some unknowns regarding the other pins that need to be hooked up to properly connect an internal pcie device, since there are a handful of pins required besides just power, ground, and the four pins per lane (rx pair and tx pair). but i should be able to wing it and literally start to wire up a 3rd party gpu and try to get it to boot (the vega frontier or s9000). as long as i'm not inverting or shorting power a bad hookup would cause the pcie device to not be successfully recognized or to be recognized but not usable. at worst a bad hookup would cause the entire boot to fail but still not cause any permanent damage to either the pcie device or the mac pro 2013. hopefully.

front layer 01


front layer 03


back layer 01 (image flipped horizontally)


back layer 03 (image flipped horizontally)

 

[CodeJingle]

pcie 4 will only need 8x for same speed as pcie 3 x16. pcie 5 will only need 4x for same speed as pcie 3 x16 and so a thunderbolt gen 5 connection to egpu would make everyone happy (if thunderbolt 5 is internally driven at pcie 5 x4). you might say a better gpu will require more throughput, but i've heard pcie 5 is not designed to drive a single device at x16. pcie 5 is not in sight and even for widespread adoption of pcie 4 is maybe five years away.

this is still besides the point that apple purposefully obfuscating pcie is counterproductive as long as thunderbolt continues to be a layer on top of pcie. unless apple plans to create custom low level IP that completely replaces the pcie standard.

to get apple's attention, the core argument here should be selfless and affect apple's bottom line. apple has a big problem finding A, even B+, talent. they are going to education to create the talent. apple also needs expertise. i'm sure apple could use another senior dev for pcie, and would prefer to not teach the new hire pcie from scratch as part of the ramp-up process. apple is destroying the pcie dev community. in this case apple is the cause of their own problem. the highest end mac pro should encourage developers/engineers to learn and use pcie instead of suppressing it. it doesn't force non-developer professionals to have to learn pcie, but it also doesn't stop those who do want to learn pcie hardware. if apple wants engineers that don't suck, they need to make machines and operating systems that allow developers to exercise the standards directly (like pcie), while simultaneously hand holding and hiding the same functionality from non-engineer/non-developer professionals. 'thunderbolt or pcie' should be the norm not 'thunderbolt only'.

 

[CodeJingle]

if you look at the first few posts of the thread, i am already delayering boards and trying to understand pcie at a more fundamental or 'bare metal' level. In that aspect the thread hasn't changed.

poisonous pcie adapter board that ignited/exploded when i depopulated it





nvidia 8x gpu



[doublepost=1527555093][/doublepost]for the last two signal layers of the mac pro 2013 logic board, the board will literally start to fall apart. so i had to add some coatings to one side of the board and let it dry so that when i bore into the last layer of the board it can hang onto the coatings instead of crumbling in my hands. letting it dry for 24+ hours before finishing delayering.

 

[CodeJingle]

i ordered two le grand macho heatsinks, more thermal potting epoxy, and a 1st gen htc vive set (still getting second vega gpu and vive pro, but later). they should all come this weekend. i'll see what i can do by the keynote on monday if anything.

i wouldn't assume anything so set expectations low. not for failure necessarily but that delayed shipment or in general the ongoing theme that this all takes alot of time and something still wouldn't be ready to show by monday 10am pt.

 

[crhendo]

Hi all,

I have just upgraded to High Sierra 10.13.5 with my NVMe Samsung 960 Pro on my Mac Pro 6,1 and was hoping that somebody (without NVMe installed) could confirm that the following Boot ROM version is the same as they have after the upgrade. Many thanks in anticipation......

Boot ROM Version: MP61.0123.B00

SMC Version (system): 2.20f18

Illumination Version: 1.4a6

 

[tanoanian]

Hi all,

I have just upgraded to High Sierra 10.13.5 with my NVMe Samsung 960 Pro on my Mac Pro 6,1 and was hoping that somebody (without NVMe installed) could confirm that the following Boot ROM version is the same as they have after the upgrade. Many thanks in anticipation......

Boot ROM Version: MP61.0123.B00

SMC Version (system): 2.20f18

Illumination Version: 1.4a6

I didn't have the patience when 10.13.6 beta was posted first but here's mine on .6

Boot ROM Version: MP61.0123.B00
SMC Version (system): 2.20f18
Illumination Version: 1.4a6

 

[CodeJingle]

was hoping that somebody (without NVMe installed) could confirm that the following Boot ROM version is the same

if certain macos upgrades require reverting the internals to stock hardware, that is a shame and will put many off to the idea of upgrading their machine past the max stock configuration. i sold my stock ssd now i think i need to buy a replacement at least on the low end just for upgrades. pain in my rump. as a software and hardware engineer it seems a reasonable level of difficulty (not super easy but also not that hard) to formally support nvme on mac pro 6,1. they already support nvme on imac pro. i must be missing something here.