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Qualcomm Nuvia vs Apple Mx
- Thread starter crazy dave
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- amd apple silicon intel nuvia qualcomm
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Not with that kind of performance, unfortunately. I hope that Phoenix ends up at least 20-30% faster. It's a 2024 product after all.
The gains from Gen3 to Gen4 are really tiny considering that Nuvia cores are completely custom, and they're using N3.
It seems to me its more a question if Qualcomm’s Nuvia-powered products can carve a niche out of the Wintel laptop market, based on performance and battery life. If people don’t see a clear advantage to buying them, it’s going to eventually be a non-starter as a commercial product.
Comparisons to Apple’s M-series chips are no more than a marketing ploy, Apple’s market is MacOS laptops and because they control the OS there won’t be much competition there. At most similar-performing laptops will stem the tide of switchers from PC.
Apple’s laptop performance lead comes in two main forms, low-end laptops with killer single-threaded performance at the 1000 dollar price point, and premium laptops with great all-around performance and battery life at the 2500 dollar price point. If Qualcomm are going to provide one SoC they have to decide where to price it for the OEMs.
And wasn’t there a lawsuit by Arm?
Since the testing methodology itself changed between GB5 and GB6, there really isn't an easy way to convert scores from 5 to 6 or vice-versa.
It usually takes years from RAM standard ratification to commercial availability a d LPDDR6 isn’t even ratified yet.
Does any of these figures have merit?
Does it make sense that M3 wins in single-core by such a margin to Qualcomm's SoC, but loses in multi-core?
What configuration could 8cx have to reach 1800 in single-core and 14000 in multi-core?
What configuration could M3 have to reach 2500 in single-core and 11000 in multi-core?
Would such a leap between M2 and M3 be possible?
Does it make sense that M3 wins in single-core by such a margin to Qualcomm's SoC, but loses in multi-core?
What configuration could 8cx have to reach 1800 in single-core and 14000 in multi-core?
What configuration could M3 have to reach 2500 in single-core and 11000 in multi-core?
Would such a leap between M2 and M3 be possible?
Yes.
Here’s my calculation for M3 GB5:
I calculated to 2600. Just 100 of the tweet. But maybe the Pro or Max versions can reach 2600.
Not every new rumour regarding a competitor means Apple could be in trouble lol
Didn't the same person previously claim ~ 2100 GB5 score for the phone Snapgradon 8 Gen4? Why would the laptop chip be that much slower?
To your other questions, sure, there can be a disparity in single core and multi-core ratio if one chip has more lower-performance cores (which would boost the multi-core score). And sure, a 30% performance improvement over M2 is probably realistic (if optimistic) for a new u-arch on 3NM node. But honestly, I don't trust any of these numbers.
The person who posted that doesn't have any merit. let alone the junk they post as "fact"...
30% is a tad optimistic but totally realistic. We have to remember that M2 is using A15 and A16 is 13% faster than A15 in ST already. A17 is two core generations ahead of A15 and one major node leap.
One of the problems is that N3B only gives a very small shrink to SRAM and N3E gives none for all practical purpose. A large chunk of transistors is used for memory so don’t expect much die shrinkage if any.
And that’s where the new fancy patents about die stacking come in
I suspect that at some point it’s cheaper to manufacture half of the system on 5nm and pay for advanced packaging rather than try to fit it all on a single 3nm die…
Well, N3 probably allow Apple to clock their caches higher. As it is now, M2 running at 3.5GHz is still slower than what LPDDR4X-4266 can push, never mind LPDDR5. I suppose their cache sizes is big enough and likely no need to go much higher.
Does it even work like that? I thought that cache and CPU frequency had to be somehow matched? My impression was that improvements to cache bandwidth usually come from wider cache path (e.g. M1/M2 can only fetch 48 bytes/cycle from L1 while Intel can do whopping 128 bytes/cycle with AVX-512.
I am genuinely asking, I really don't know.
My understanding is that cache and CPU clock has to match too, so that means CPU clock will also increase.
The problem is that when RAM bus clock is different from CPU cache clock, delays has to be inserted, once data starts bursting from RAM. Once data is in cache, it's basically low latency fast memory, but it needs to be fetched from RAM first.
It's been a long time since my logic design course tho.