Could we see M3 before A17?

[steve123]

wouldn't that mean that Apple should use the same node for A17 and M3? Which node will A17 use?

Not necessarily. The use of any particular node depends in part on when the node becomes available and the design cycle. N3 came first and so Apple would have made a design cycle decision three or four years ago to target that node with certain designs. Remember, these designs take years of effort and building the fabs to manufacture them take years as well. M3 and M4 designs are going on in parallel and are staggered in time by one year and TSMC builds fabs in parallel and staggers their production launch by one year. So, the M3 design cycle does not end before M4 begins. M4 already began years ago now. In fact, there are already M4 prototypes being evaluated by the design team.

TSMC would have made the financial decision to proceed with the $10B expense of building the fab based in part because of the interest from Apple. N3E came after N3 so decisions by Apple about which products to target the N3E node were probably made a year or more later.

If A17 and M3 roadmaps intersected with N3 at the same time, they would use the same node. This is very likely the case. N3E will in all likelihood be the node targeted for the next iteration, A18 and M4.

 

[Xiao_Xi]

If A17 and M3 roadmaps intersected with N3 at the same time, they would use the same node. This is very likely the case. N3E will in all likelihood be the node targeted for the next iteration, A18 and M4.

If Apple uses N3 for M3, wouldn't it be in an awkward position if AMD and Nvidia use N3E (better and cheaper than N3) for their products in 2024?

 

[deconstruct60]

Cost isn't what is holding others away from N3 but actual production capacity. Apple have bought all the capacity for N3 at TSMC if rumours are to be believed.

Rumors back in March said that while capacity was expected to expand to 45K wafers/month by end of March , actual utilization was only going to get to 50%. That means only about 24K wafers/month were going through. That means Apple is not bought out all of the capacity. The system isn't 3/4 full at this point.

Apple has bough enough so that if someone else needed a very large order of wafers perhaps there is not enough to go around. But "all" the capacity? Nope.

If there was someone who needed a steady flow of 4K wafers a month, but Apple's demand bubble in June-August for iPhone chips was going to squeeze that out of the avaialable capacity they might wait until after the bubble to go. ( depending upon when they needed to introduce a new product). 2-4K wafers a month isn't going to move TSMC revenue numbers much so won't get talked up in these quarterly financial conference calls or ad-click bait rumor articles.

 

[steve123]

If Apple uses N3 for M3, wouldn't it be in an awkward position if AMD and Nvidia use N3E (better and cheaper than N3) for their products in 2024?

Good point, maybe, but Apple will release M4 in 2024 on N3E.

 

[dmccloud]

If Apple uses N3 for M3, wouldn't it be in an awkward position if AMD and Nvidia use N3E (better and cheaper than N3) for their products in 2024?

With Apple locking up N3x production for at least a full year, that puts everyone else behind Apple in TSMCs production queues. Assuming Apple's approach holds true, they would probably lock up the initial run of N3E as well so that once the N3 exclusivity runs out, they have N3E to themselves for the time being. At that point, N3 capacity would open up for AMD, nVidia, etc.

 

[Xiao_Xi]

Assuming Apple's approach holds true, they would probably lock up the initial run of N3E as well so that once the N3 exclusivity runs out, they have N3E to themselves for the time being.

If Apple uses N3 for the future SoC of iPhones, iPads and Macs, which SoC would Apple manufacture with N3E in late 2023/early 2024?

Apple will release M4 in 2024 on N3E.

Could Apple be forced to upgrade all Macs with N3-based M3 in 2023 and N3E-based M4 in 2024 to keep the node advantage? Wouldn't it make more sense for Apple to use N3 for A17 this year and N3E for M3 next year?

 

[jdb8167]

If Apple uses N3 for M3, wouldn't it be in an awkward position if AMD and Nvidia use N3E (better and cheaper than N3) for their products in 2024?

I think N3E is cheaper with better yields but it isn’t better overall. You get lower power and a slight increase in density with N3B if I remember correctly.

Edit: You get higher density with N3B but not better performance. So yes, N3E will be better overall. But it isn’t going to be available until at least Q3 and probably later.

 

[steve123]

Could Apple be forced to upgrade all Macs with N3-based M3 in 2023 and N3E-based M4 in 2024 to keep the node advantage?

Yes but I think we may see a strategy evolve with Macs similar to the iPhone, iPad and Watch. The new node will launch in the Pro Max Ultra line of products first and the base models will use the prior generation. This implies that base models of MBA, Mini, iMac and Studio may not receive an update to M3 until the fall of 2024. This might be contributing to confusion about Mark Gurman's comments of M2 sticking around for a little while longer.

Wouldn't it make more sense for Apple to use N3 for A17 this year and N3E for M3 next year?

Only if Apple wants their Pro Max Ultra line of products to be a year behind. That would give their competition bragging rights for an entire year and that does not make any sense to me.

 

[steve123]

Assuming Apple's approach holds true, they would probably lock up the initial run of N3E as well so that once the N3 exclusivity runs out, they have N3E to themselves for the time being.

Indeed, I believe this is their strategy.

 

[senttoschool]

I think N3E is cheaper with better yields but it isn’t better overall. You get lower power and a slight increase in density with N3B if I remember correctly.

Edit: You get higher density with N3B but not better performance. So yes, N3E will be better overall. But it isn’t going to be available until at least Q3 and probably later.

N3B is slightly better because you can pack more transistors in the same space and the SRAM scaling is 5% better than 5NM while N3E has no gains.

That's why I assumed all along that Apple would use N3B for both A17 and M3.

 

[Xiao_Xi]

N3B is slightly better because you can pack more transistors in the same space and the SRAM scaling is 5% better than 5NM while N3E has no gains.

At IEDM 2022, TSMC revealed some aspects of N3B. [...] TSMC also demonstrated a 6-transistor high-density SRAM bit-cell of 0.0199 μm2. This is only a 5% shrink, which bodes poorly for SRAM scaling into the future.

During IEDM, TSMC revealed that N3E had a bit-cell size of 0.021 μm2, precisely the same as N5. This is a devastating blow to SRAM. TSMC backed off of the SRAM cell size versus N3B due to yields.

TSMC’s 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed

Shrinking finally costs more, Moore’s Law is now dead in economic termsA couple of weeks ago, we were able to attend IEDM, where TSMC presented many details about their N3B and N3E, 3nm class…

www.semianalysis.com

Out of curiosity, is it necessary to redesign for N3E the SoCs designed for TSMC N3?

Unlike the previous nodelets that TSMC has launched for its N7 and N5 family of nodes, N3E is not IP-compatible with N3B IP. This means that IP blocks have to be reimplemented.

TSMC’s 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed

Shrinking finally costs more, Moore’s Law is now dead in economic termsA couple of weeks ago, we were able to attend IEDM, where TSMC presented many details about their N3B and N3E, 3nm class…

www.semianalysis.com

TSMC FINFLEX™ – Ultimate Performance, Power Efficiency, Density and Flexibility - Taiwan Semiconductor Manufacturing Company Limited

Many product designs are a series of compromises. Take for example, electric vehicles, wouldn’t it be great to have a 1000-mile or 1600-kilometer range in an EV? But consider what compromises would need to be made to achieve this goal. The battery would be massive and heavy, leading to an...

www.tsmc.com

Could it make sense for Apple to use N3E 2-1 for Ax and N3E 2-2 for Mx?

 

[Pressure]

TSMC’s 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed

Shrinking finally costs more, Moore’s Law is now dead in economic termsA couple of weeks ago, we were able to attend IEDM, where TSMC presented many details about their N3B and N3E, 3nm class…

www.semianalysis.com

TSMC’s 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed

Shrinking finally costs more, Moore’s Law is now dead in economic termsA couple of weeks ago, we were able to attend IEDM, where TSMC presented many details about their N3B and N3E, 3nm class…

www.semianalysis.com

View attachment 2192391

TSMC FINFLEX™ – Ultimate Performance, Power Efficiency, Density and Flexibility - Taiwan Semiconductor Manufacturing Company Limited

Many product designs are a series of compromises. Take for example, electric vehicles, wouldn’t it be great to have a 1000-mile or 1600-kilometer range in an EV? But consider what compromises would need to be made to achieve this goal. The battery would be massive and heavy, leading to an...

www.tsmc.com

Could it make sense for Apple to use N3E 2-1 for Ax and N3E 2-2 for Mx?

I think you are missing the point of FINFLEX.

You can have them all for different blocks on the same die. So performance cores can use 3-2 Fin, efficiency cores can use 2-2 Fin and the GPU as well as the neural engine 2-1 Fin or whatever your performance targets are for the different blocks.

 

[dgdosen]

From this EETimes article (https://www.eetimes.com/tsmcs-3-nm-push-faces-tool-struggles/):

That means a yield of around 620 chips per wafer with a wafer cycle time of four months, the report added. M3 is likely to be around 135-150 mm square die size and around 450 chips per wafer

Another thread is showing TSMC is "monthly output set to reach 45,000 wafer in March". (https://www.macrumors.com/2023/02/22/apple-secures-tsmc-3nm-chips/)

Say 45,000 wafers, split 5,000 for M chips, and 40,000 for A chips:

5,000 wafers * 450 chips/wafer = 2,250,000 chips
40,000 wafers * 620 chips/wafer = 24,800,000 chips

all of that is per month! Well exceeding Apple's mac/iphone sales, even with long cycle times.

 

[steve123]

Say 45,000 wafers, split 5,000 for M chips, and 40,000 for A chips:

5,000 wafers * 450 chips/wafer = 2,250,000 chips
40,000 wafers * 620 chips/wafer = 24,800,000 chips

Those numbers are total chips per wafer and the cycle time is 4 mo (1/3 year). The yield is 55% at the moment so quarterly volume numbers should 41.25%:
928,000 x M3
10,230,00 x A17

M3 Pro Max Ultra are larger die so M3 numbers are likely lower.

 

[dgdosen]

Those numbers are total chips per wafer and the cycle time is 4 mo (1/3 year). The yield is 55% at the moment so quarterly volume numbers should 41.25%:
928,000 x M3
10,230,00 x A17

M3 Pro Max Ultra are larger die so M3 numbers are likely lower.

I'll agree that the numbers probably didn't include a reduction for yield (even though the article says yield in the description, so those numbers should drop to the 55%

But the other article mentions "monthly output" - so I'm assuming there's about 4 months of inventory in WIP. So the question is, how many wafers can be in process in a given month? 45,000? or 180,000?

 

[Tagbert]

Today’s article is another suggestion that the M3 will not be here before the end of the year.

TSMC Struggling to Make Enough 3-Nanometer Chips for Apple

Apple supplier TSMC is "straining" to produce enough of its newest 3-nanometer chips to meet demand for Apple's upcoming devices,...

www.macrumors.com

 

[steve123]

But the other article mentions "monthly output" - so I'm assuming there's about 4 months of inventory in WIP. So the question is, how many wafers can be in process in a given month? 45,000? or 180,000?

Right, you said per month. I went back and looked into the wafer starts per month. I cannot find anything from TSMC that says that. They indicated a couple months back that the new fabs in Arizona will reach about 50000 wafer starts per month (for two fabs, so 25000 per month per fab).

It looks like the source of the 45000 number is a Digitimes report quoted here on macrumors:

Apple Orders Entire Supply of TSMC's 3nm Chips for iPhone 15 Pro and M3 Macs

Apple has reportedly secured all available orders for N3, TSMC's first-generation 3-nanometer process that is likely to be used in the upcoming...

www.macrumors.com

and that article says "eventual production". The EETimes article says TSMC will put ASML’s NXE:3800E EUV into production in second half, so, this reduces max capacity in 1H by 30% to 34600 wafer starts per month. Based on the Arizona numbers, those wafer starts might be for N3 and N3E combined. So, N3 might only be 1/2 that. So, 17300 per month. And of course, there is a ramp since you start at 0 and cycle time is 4 months. So, average 0.5x for the first 4 mo. Assume 90/10 split A17 to M3.

A17:
17300 x 0.9 x 8mo * 620 * 55% = 42.5M by end of Sep.
Likely sufficient for iPhone 15 Pro Max Ultra launch

M3:
17300 x 0.1 x 5mo x 450 x 55% = 2.1M by end of June
Likely sufficient for Mac Pro launch

 

[senttoschool]

M3:
17300 x 0.1 x 5mo x 450 x 55% = 2.1M by end of June
Likely sufficient for Mac Pro launch

You're not going to get 450 Ultra/Extreme chips from one wafer. I'm guessing they'll get less than 100 Ultra chips per wafer. Also, they can't launch any Ultra/Extreme chips until they make an M3 Max.

 

[steve123]

You're not going to get 450 Ultra/Extreme chips from one wafer. I'm guessing they'll get less than 100 Ultra chips per wafer. Also, they can't launch any Ultra/Extreme chips until they make an M3 Max.

Ultra is an SiP using two Max chips. Do not know from the EETimes article what the size of Pro and Max are but they gave a range. The chips per wafer is calculated using the larger size in the range.

 

[senttoschool]

Ultra is an SiP using two Max chips. Do not know from the EETimes article what the size of Pro and Max are but they gave a range. The chips per wafer is calculated using the larger size in the range.

I wrote how you can calculate chips/wafer here: https://forums.macrumors.com/threads/could-we-see-m3-before-a17.2382874/post-32098242

Just use the dimensions of M1/M2 Max. It's not going to deviate too much.

And yes, Ultra is 2x Max. That's what I said. You need to make a Max before an Ultra/Extreme.

 

[Xiao_Xi]

5,000 wafers * 450 chips/wafer = 2,250,000 chips
40,000 wafers * 620 chips/wafer = 24,800,000 chips

Will all these chips be good enough to be in a Mac? Is there any information on binning?

By the way, is it true that TSMC N3(B) is the "true" 3 nm node and TSMC N3E is more like TSMC N4?

 

[dmccloud]

If Apple uses N3 for the future SoC of iPhones, iPads and Macs, which SoC would Apple manufacture with N3E in late 2023/early 2024?


Could Apple be forced to upgrade all Macs with N3-based M3 in 2023 and N3E-based M4 in 2024 to keep the node advantage? Wouldn't it make more sense for Apple to use N3 for A17 this year and N3E for M3 next year?

The node advantage comes from booking the production capacity, which is independent of releasing updated Macs.

Ultra is an SiP using two Max chips. Do not know from the EETimes article what the size of Pro and Max are but they gave a range. The chips per wafer is calculated using the larger size in the range.

According to Tom's Hardware, the M1 is roughly 118 sq mm, M2 Max roughly 432 sq mm, and the M1 Ultra ~860 sq mm. Since the base M2 is on a larger die than the base M1 (155 sq mm for the M2 compared to 118 sq mm for the M1), the M2 Pro, Max and Ultra SoCs should also scale accordingly. That would theoretically put the M2 Ultra at around 1100-1130 sq mm in size, although that's just a guess until we actually see confirmation that an M2 Ultra even exists.

 

[steve123]

That would theoretically put the M2 Ultra at around 1100-1130 sq mm

My understanding is Ultra is not a single monolithic chip. Rather a System in Package with two Max die connected within the same package using UltraFusion interconnect?

 

[Wokis]

My understanding is Ultra is not a single monolithic chip. Rather a System in Package with two Max die connected within the same package using UltraFusion interconnect?

I don't recall who said what I'm about to, so take it with lots of grains of salt before hopefully someone in the know replies.

My understanding is that the "interconnect" is so intricate that it doesn't really work for connecting two random Max chips together at an assembly stage. As I recall it they have to be "printed" together, next to each other with the silicon interconnect, on the wafer. If one die has a defect, they get detached and at least one half of it gets sold off as a Max.

 

[steve123]

I don't recall who said what I'm about to, so take it with lots of grains of salt before hopefully someone in the know replies.

My understanding is that the "interconnect" is so intricate that it doesn't really work for connecting two random Max chips together at an assembly stage. As I recall it they have to be "printed" together, next to each other with the silicon interconnect, on the wafer. If one die has a defect, they get detached and at least one half of it gets sold off as a Max.

My understanding about what makes the interconnect unique is that it is fabricated using chip making processes as compared of conventional chip packaging techniques that involve processes similar to circuit boards. The precision of the chip process and because the interconnect is a silicon substrate ensures the pads connecting the interconnect with the die align properly and minimizes thermal stress.

It interesting thought regarding this technique is since the interconnect is a silicon process, if it is also a CMOS compatible process then Apple may have the ability to incorporate some logic functions with the interconnect. I wonder if the do such?