M3 Chip Generation - Discussion Megathread

[nquinn]

There are probably 2 reasons:

1. MacBook Air 15" was just released 4 months ago. It's way too early to update it to M3. Buyers of the M2 15" Air would feel terrible. It doesn't make sense to update the 13" to M3 and not the 15" at the same time.

2. Because of the lower yields of N3B, Apple may not have enough base M3 chips to launch Air updates. This is assuming M3 is using N3B because A17 Pro is using N3B and because N3E is scheduled for volume production in "H2 2023" which is a little too late for volume M3/Pro/Max launch.

I personally think that Apple was planning to use M3 for the 15" Air launch at WWDC. Something unexpected must have happened and they couldn't pull it off. It's hard to explain why the M3, M3 Pro, and M3 Max are launching together at the same time.

The 15" air should have come with the M3. M2 is so old at this point it was kind of insulting for them to do that.

In reality I think Apple may shift to the higher end machines getting the newer cpu's first (macbook pros) and then the other devices getting it to follow later (macbook air, mac mini, imac, etc).

Kind of opposite of how the cpus are usually produced though.

 

[leman]

Kind of opposite of how the cpus are usually produced though.

There is no common order to how the CPUs are released. In Apple case, it makes a lot of sense to focus on high-end models first, to better utilise limited production capability of the foundry as well as absorb the higher costs of the new process node. Not to mention that it makes more sense psychologically.

Trying to release the entire model range using the 3nm process right now would lead to an epic supply disaster.

 

[T'hain Esh Kelch]

There are probably 2 reasons:

1. MacBook Air 15" was just released 4 months ago. It's way too early to update it to M3. Buyers of the M2 15" Air would feel terrible. It doesn't make sense to update the 13" to M3 and not the 15" at the same time.

There's nothing holding Apple back from updating the 13” model only, and then the 15” model in spring.

 

[Confused-User]

There is no common order to how the CPUs are released. In Apple case, it makes a lot of sense to focus on high-end models first, to better utilise limited production capability of the foundry as well as absorb the higher costs of the new process node. Not to mention that it makes more sense psychologically.

Trying to release the entire model range using the 3nm process right now would lead to an epic supply disaster.

You know, everyone says that, but based on what data? My impression is that TSMC has an oversupply of wafers because everyone else except a couple of crypto-chip makers (very low wafer volume; the dice are tiny) passed on N3B. But like everyone else I'm just trying to read between lines that are exceptionally blurry.

So, let's look at some numbers. ...ok, let's not, because I can't find them readily. And asking bing's AI produced a stream of lies, which in itself was pretty interesting (it confused the A16 and the M2!). What I wanted to do was:

1) Compare size of M2 and A15. Call the relative increase in die area X.
2) Multiply size of A17 by X to get a rough estimate of the area of the M3. (Very rough, but adequate for our purposes.)
3) From that produce an even rougher guess of the M3 Pro and Max areas.
4) Get a rough estimate of anticipated sales volume for the M3P/M-based MacBook Pros, based on historical figures for previous MBP releases.
5) Figure how many A17s would be sacrificed to instead supply M3P/M chips based on die areas
6) Use weekly sales volume figures for the iPhone 14 Pro/Max to estimate same for 15s, then figure how much of an impact, measured in weeks of delay, shipping M3s would have on iPhone supply. Of course this assumes that chip supply is actually the limiting factor (which, I'll note, is not known to be true).

The A15 is about 108mm^2. The M2 is about 142mm^2. The A17 is about 105mm^2. That part was easy. But then I got bogged down in sales figures, broken down by quarter, for which there are many conflicting numbers (which apparently utterly confused bing, when I asked it for help). Now I'm out of time, but if anyone else wants to complete this, I'd be curious to see what they come up with.

My instinct is that the additional backlog in iPhone 15 Pro shipping time would not be meaningful, but I can't (yet) support that with evidence. And again, this all assumes that chip supply is even an issue, and I seriously doubt that.

 

[MayaUser]

• M3: The central processing unit will boast eight cores (four for handling high-performance tasks and four efficiency cores focused on background functions) and as many as 10 cores for processing graphics. That matches the counts of the M2, but the M3 will likely support improved memory configurations and get far faster performance from each core.
• M3 Pro: This chip has been tested in multiple configurations, including one with 12 CPU cores (six for performance and six for efficiency) and 18 graphics cores. Higher-end versions of the M3 Pro are likely to get 14 CPU cores and 20 graphics cores.
• M3 Max: This chip has also been tested in different configurations, including one with 16 CPU cores (12 for performance and four for efficiency) and a whopping 40 graphics cores. There also was a less powerful version that had a still-ginormous 32 graphics cores

 

[Populus]

Just 18 hours to know what’s all about the new gen Apple Silicon!

I’m really curious about wether the big jump in performance will happen with the M3, or rather with the M4 gen. We’ll see!

 

[leman]

You know, everyone says that, but based on what data? My impression is that TSMC has an oversupply of wafers because everyone else except a couple of crypto-chip makers (very low wafer volume; the dice are tiny) passed on N3B. But like everyone else I'm just trying to read between lines that are exceptionally blurry.

You make some good point but isn't there also some circumstantial evidence that 3nm might be in short supply? Such as reports of lower yields, the fact that Apple splits chip production between the base 15 and 15 Pro (and the later is still backlogged)...

Of course, as you say, this is all just speculation. Maybe there is no bottleneck and it's all just marketing/business reasons or maybe the bottleneck lies elsewhere (e.g. packaging?)

 

[T'hain Esh Kelch]

You know, everyone says that, but based on what data? My impression is that TSMC has an oversupply of wafers because everyone else except a couple of crypto-chip makers (very low wafer volume; the dice are tiny) passed on N3B.

I think most rumors have stipulated that TSMC had production ramp problems in the beginning, but on the other hand, they should have started volume production a year ago, so it could go both ways I guess.
Rumors have also been quite clear that Apple has about a year of exclusivity on TSMCs 3nm production, so I don't think they have an oversupply at all. Apple takes everything they can produce. And I've never heard about the crypto link - Are you sure you aren't thinking about Samsungs 3nm production, which have been said to lack customers, but have been found in crypto mining units?

 

[treehuggerpro]

As per @T'hain Esh Kelch , there's discussion on yields at TSMC/Apple’s N3B here from the SemiWiki guy (Daniel Nenni). 24:50m - 29:00m. Posted in May.

 

[senttoschool]

Just 18 hours to know what’s all about the new gen Apple Silicon!

I’m really curious about wether the big jump in performance will happen with the M3, or rather with the M4 gen. We’ll see!

I'm also very curious. I've been debating to myself whether I should wait until M4 or not before I upgrade my M1 Pro. I have this suspicion that M4 won't have as many new features as M3 but it will have more cores and better speed/efficiency. I suspect that Apple wanted to stay fairly conservative with M3 due to the transition to 3nm.

 

[Confused-User]

You make some good point but isn't there also some circumstantial evidence that 3nm might be in short supply? Such as reports of lower yields, the fact that Apple splits chip production between the base 15 and 15 Pro (and the later is still backlogged)...

Of course, as you say, this is all just speculation. Maybe there is no bottleneck and it's all just marketing/business reasons or maybe the bottleneck lies elsewhere (e.g. packaging?)

TSMC was saying as early as late last year that their yields were good. The only contrary reports have been poorly sourced and extremely vague. I think the only reason they were given any credibility at all is that Apple didn't ship M3s when many (including me!) expected them to, in the spring. And also, that other TSMC customers didn't use the node, but given the incompatibility with N3E, that actually supports the notion that availability isn't the issue at all - if it were, a bunch of vendors would simply be shipping late, not on N3E.

As for Apple not shipping A17P in the iP15, well, that sucks, but I think Apple has simply decided that they like having a stronger upsell. After all, the A16 was still the performance leader, so they don't really feel a ton of pressure. (Hopefully QC can tighten the screws a bit more over the next year... we'll see.)

Rumors have also been quite clear that Apple has about a year of exclusivity on TSMCs 3nm production, so I don't think they have an oversupply at all. Apple takes everything they can produce.

Not at all - rumors were very unclear. My takeaway was that TSMC had overplayed their pricing hand, and wound up with a glut by the summer. They were *trying* to get Apple to take it all, even at a lower price, because everyone else had walked away from it in favor of the later cheaper N3E. And it sure looks like that's how it worked out, doesn't it?

And I've never heard about the crypto link - Are you sure you aren't thinking about Samsungs 3nm production, which have been said to lack customers, but have been found in crypto mining units?

You're correct about that, I mixed those two up. Has no bearing on the point I'm making though.

 

[Confused-User]

I'm also very curious. I've been debating to myself whether I should wait until M4 or not before I upgrade my M1 Pro. I have this suspicion that M4 won't have as many new features as M3 but it will have more cores and better speed/efficiency. I suspect that Apple wanted to stay fairly conservative with M3 due to the transition to 3nm.

The evidence so far (see here, thanks @leman!) doesn't look conservative to me. It looks moderately aggressive and highly focused on Mac performance. But I guess we'll know in 12 hours or so.

 

[Confused-User]

As per @T'hain Esh Kelch , there's discussion on yields at TSMC/Apple’s N3B here from the SemiWiki guy (Daniel Nenni). 24:50m - 29:00m. Posted in May.

Very nice, thanks. Strong confirmation that TSMC is NOT having yield issues. If he says he's seen the yield curve, I believe it.

 

[T'hain Esh Kelch]

Not at all - rumors were very unclear.

Well, that is the definition of rumors I guess.

My takeaway was that TSMC had overplayed their pricing hand, and wound up with a glut by the summer. They were *trying* to get Apple to take it all, even at a lower price, because everyone else had walked away from it in favor of the later cheaper N3E. And it sure looks like that's how it worked out, doesn't it?

How does it look like that? N3E hasn't come out yet, so no indications of anyone else using it. In fact, it looks exactly as if Apple has bought everything 3nm TSMC could produce, as they are the only one who has put anything with it on the market.

 

[Populus]

I'm also very curious. I've been debating to myself whether I should wait until M4 or not before I upgrade my M1 Pro. I have this suspicion that M4 won't have as many new features as M3 but it will have more cores and better speed/efficiency. I suspect that Apple wanted to stay fairly conservative with M3 due to the transition to 3nm.

Yep, my exact thoughts. After launching the A14, which was a really big improvement, they launched the A15 which, time has shown, was also a really significant upgrade architecture wise (new efficiency cores and double the cache), so the A16, which was also a better improvement that I initially thought, felt a bit meh, and with the A17 Pro the incremental, continuist and conservative nature of the chip is noticeable.

I think they decided to dose the 3nm improvement, so they just updated the A16 with much higher clock speeds and a new GPU architecture. I’d say that the double performance of the 16 core Neural Engine is due to this increase in clock speed.

Also, there’s the “problem” that architectures made for the N3B node don’t scale well (?) or are not very compatible (?) with the upcoming N3E process. Yeah, I’m not sure what that means, but I think it points towards a new, much better architecture for the silicon coming with the N3E process, such as the A18 and the A18 Pro chip. And I do expect a big improvement with that generation of silicon.

Wether the M3 chips are based on the A17 Pro (and made using the N3E node) or are they based on the upcoming A18 (and made using the N3E process), is the key, at least for me, to know if this M3 gen is going to be 1) as continuist and iterative as the A17 Pro, just higher clock speeds, more RAM and a more powerful GPU architecture with RayTracing, or 2) they are going to introduce a new e-core, p-core and n-core architecture as well, with higher core counts, which would be a considerable improvement on the Apple Silicon horizon.

My bet is number 1), and if that’s the case, I’ll try to wait until the M4 gen… if Taiwan keeps manufacturing chips with normality by then. But the higher RAM across the board of the M3 gen, including a bigger 12GB base memory, could trigger me buying a new mini or a 12” MacBook in 2024.

I know, I know, Mac minis or MacBook Airs or even the 12” MacBook isn’t expected today, but as I said, todays event, and soon further analysis of the M3, M3 Pro and M3 Max will give us a good hint on whether we should wait just a little bit more or not.

 

[Confused-User]

Well, that is the definition of rumors I guess.

Some rumors are clearer than others. And better sourced. In this case there's a lot of conflicting opinions from well-connected people.

How does it look like that? N3E hasn't come out yet, so no indications of anyone else using it. In fact, it looks exactly as if Apple has bought everything 3nm TSMC could produce, as they are the only one who has put anything with it on the market.

There are a TON of indications, or even outright statements- for example, AMD said they will use 3nm for Zen 5 last year. The N3 process family will be huge, and will be in wide use for years because it's the last FinFET node. Everyone and their dog will be using it for anything that needs serious performance (so: CPU, GPU, NPU cores, at the very least). In fact it may well become a super-long-term node like 28nm because the cost of doing GAA may be too high for some players to ever bother with.

Apple's been first with both N7 and N5. Didn't mean others didn't use it too. It will be the same with N3 except more so over time.

 

[leman]

Yep, my exact thoughts. After launching the A14, which was a really big improvement, they launched the A15 which, time has shown, was also a really significant upgrade architecture wise (new efficiency cores and double the cache), so the A16, which was also a better improvement that I initially thought, felt a bit meh, and with the A17 Pro the incremental, continuist and conservative nature of the chip is noticeable.

I don't think that A17 Pro is conservative in any way. The P-core gained two more int unit (a 33% increase), an additional branch unit (a 50% increase), and generally a vastly improved handling of conditional operations. The E-core has improved the FP throughput by 50%. These are all fairly massive improvements, at least in their respective area. In fact, that's bigger backend improvements than what Intel did with Alder Lake (which was widely regarded as the biggest micro architectural improvement in Intel CPUs for over a decade).

As to why we don't see a notable improvement in IPC despite all these changes, that's a different question. It is possible that Apple designs have reached the Amdahl's law limit for the common code. Or maybe there are some other bottlenecks present on the iPhone chip that might be fixed on the Mac. We should know soon enough.

What is most interesting to me though is that the new cortex X4 is allegedly as wide as A17 Pro (and in some aspects — like decode — even wider!), yet it struggles to even reach the IPC of A14.

Yeah, I’m not sure what that means, but I think it points towards a new, much better architecture for the silicon coming with the N3E process, such as the A18 and the A18 Pro chip. And I do expect a big improvement with that generation of silicon.

If we have indeed reached the parallelisation limit on most codes, I am very sceptical about future architectures delivering major IPC improvements. This leaves increasing frequency as the primary way to improve performance, or maybe a radical paradigm change and rethinking how we write code in general.

 

[leman]

There are a TON of indications, or even outright statements- for example, AMD said they will use 3nm for Zen 5 last year. The N3 process family will be huge, and will be in wide use for years because it's the last FinFET node. Everyone and their dog will be using it for anything that needs serious performance (so: CPU, GPU, NPU cores, at the very least). In fact it may well become a super-long-term node like 28nm because the cost of doing GAA may be too high for some players to ever bother with.

But in the meantime there are reports that Zen5 will use 4nm. No idea about the credibility of these rumours, link below. The mention of Zen5 on 3nm from what I understand were only made in the context of server CPUs, and it is possible that AMD will do a limited 3nm run for EPYC products only.

AMD could entirely skip TSMC's 3 nm node for consumer processors according to leaked roadmap

Industry sources cited by DigiTimes claim that all the upcoming Zen 5 processors would be manufactured on TSMC’s 4 nm nodes, with the sole exception of the 2025 EPYC processors that will feature 3 nm silicon. Zen 6 is expected to jump directly to 2 nm.

www.notebookcheck.net

 

[Confused-User]

Yep, my exact thoughts. After launching the A14, which was a really big improvement, they launched the A15 which, time has shown, was also a really significant upgrade architecture wise (new efficiency cores and double the cache), so the A16, which was also a better improvement that I initially thought, felt a bit meh, and with the A17 Pro the incremental, continuist and conservative nature of the chip is noticeable.

Only if you don't know what you're looking at. It's not exactly what I hoped for but it's clearly a major development. See leman's thread (which I linked to above already). (Edit: ...or just read his reply. His post came in just before this one.)

I think they decided to dose the 3nm improvement, so they just updated the A16 with much higher clock speeds and a new GPU architecture. I’d say that the double performance of the 16 core Neural Engine is due to this increase in clock speed.

Sorry, that's ridiculous. "just" is not an appropriate word for "much higher clock speeds and a new GPU architecture". Even more ridiculous is thinking that doubling NPU performance comes just from the clocks.

Also, there’s the “problem” that architectures made for the N3B node don’t scale well (?) or are not very compatible (?) with the upcoming N3E process. Yeah, I’m not sure what that means, but I think it points towards a new, much better architecture for the silicon coming with the N3E process, such as the A18 and the A18 Pro chip. And I do expect a big improvement with that generation of silicon.

It does not.

Scaling has nothing to do with it. Imagine you were a master toy builder and I asked you to build a detailed model of an oceanic oil rig using Legos. Assuming you have enough pieces, you get the job done. Now say I ask you to do the same thing, but using an Erector Set kit instead. You know what you have to build, but you're going to have to work out all the details all over again. The parts are different, and they fit together differently. When you're done, you have two oil rigs, both recognizably models of the real thing, but... they still look different. N3B and N3E are like that - you can use either to build your chip, but you need to do each one differently, and the results will be (at least) slightly different.

Your expectation for A18 may or may not come true, but it has little to do with what we're seeing with the A17, except inasmuch as every generation is the result of Apple's iterative process and the previous generation.

Wether the M3 chips are based on the A17 Pro (and made using the N3E node) or are they based on the upcoming A18 (and made using the N3E process), is the key, at least for me, to know if this M3 gen is going to be 1) as continuist and iterative as the A17 Pro, just higher clock speeds, more RAM and a more powerful GPU architecture with RayTracing, or 2) they are going to introduce a new e-core, p-core and n-core architecture as well, with higher core counts, which would be a considerable improvement on the Apple Silicon horizon.

Assuming we actually do get M3s today, it is ABSOLUTELY CERTAIN they are based on N3B. It is also an absolute certainty that they will be based on the A17 cores. Those cores look like they were designed more for Macs than for phones (though not so much that they became ill-suited for phones).

[...]I know, I know, Mac minis or MacBook Airs or even the 12” MacBook isn’t expected today, but as I said, todays event, and soon further analysis of the M3, M3 Pro and M3 Max will give us a good hint on whether we should wait just a little bit more or not.

I doubt you will know anything more about the M4 after the M3 reveal than you do now.

 

[Populus]

If we have indeed reached the parallelisation limit on most codes, I am very sceptical about future architectures delivering major IPC improvements. This leaves increasing frequency as the primary way to improve performance, or maybe a radical paradigm change and rethinking how we write code in general.

That’s a very interesting question. I know this has little to do with what we’re talking, but yesterday I saw a video of Digital Foundry where they commented on the new Unreal Engine 5.2 and how developers are implementing it on games such as sequel of The Talos Principle (great game, I 100% recommend it).

They showed how the parallelisation could be one of the causes that the engine struggles sometimes, because even in 8 core 16 thread CPUs, only two cores are being taxed heavily at 99% while the others remained at 40 or 60%.

Look, I’m not a developer, I don’t know how to code, but I’m wondering if we cannot go deeper in parallelizing the code among different cores. Maybe the coder doesn’t even need to tweak the code and can be done from the developing tools such as Xcode, but I definitely think that we should take more advantage of the different cores on the different architectures. I know, I’m sure it’s easier said than done. And maybe as you say, it’s no longer possible to optimize the code because we have reached a wall.

By the way, thank you as always for sharing your knowledge, I’m sure you’ll be expectant as to what is revealed tonight about the M3. We all are. I look forward to your new research as soon as more data on the M3 is released!

And, as always, thank you for your respectful reply, unlike the one from @Confused-User. I mean, you can like it whatever you want, but I just can’t deal with certain tones on this forum, despite the useful info his message may contain.

PS: I guess by FP you mean floating point right? Sorry I’m not too familiar with technical terminology.

 

[Confused-User]

But in the meantime there are reports that Zen5 will use 4nm. No idea about the credibility of these rumours, link below. The mention of Zen5 on 3nm from what I understand were only made in the context of server CPUs, and it is possible that AMD will do a limited 3nm run for EPYC products only.

AMD could entirely skip TSMC's 3 nm node for consumer processors according to leaked roadmap

Industry sources cited by DigiTimes claim that all the upcoming Zen 5 processors would be manufactured on TSMC’s 4 nm nodes, with the sole exception of the 2025 EPYC processors that will feature 3 nm silicon. Zen 6 is expected to jump directly to 2 nm.

www.notebookcheck.net

I won't say I'm certain they're wrong (nobody outside AMD could do that) but it seems fairly improbable.

1) If they do a core design for 3nm, why would they want to redo the whole thing for 4nm? It's not a die shrink, it's a bunch of work. Not to mention the rest of the CCX.
2) What does this buy them? Larger and hotter dies?

But there are counterarguments, maybe.
1) Doing cache in N3E instead of N4 gets no area advantage at all and it costs more. I don't know if you can reasonably stack an N4 cache chiplet on top of an N3E CCX - I don't see why not, but I don't know enough about the tech and could be missing something blindingly obvious. If you can't, that could possibly be an argument in favor of N4.
2) AMD could (reasonably or not) have fears about sufficient supply. Such constraints have definitely hobbled them in the past, so they might be being cautious here.

I still think it's unlikely. What's more likely is the CCXes are being done in N3E and the I/O die is being done in N4 - and maybe stacked cache too, if that's feasible. I can easily imagine some half-clueful reporter mixing this up.

(Edit: And if they have another chiplet too, like an NPU or other special accelerator, that could be in N4. As could, maybe, any "c" (efficiency) cores like the ones in the Bergamo- though that's less obvious.)

 

[leman]

PS: I guess by FP you mean floating point right? Sorry I’m not too familiar with technical terminology.

Yes, floating point. Sorry, I should have been more clear. Usually it's me who is getting annoyed about opaque abbreviations.

 

[leman]

1) If they do a core design for 3nm, why would they want to redo the whole thing for 4nm?

Maybe the potential payout from having more efficient and faster server cores is higher than the cost of new layout and retooling? And maybe the consumer cores wouldn't benefit much (or the price/availability would make them less competitive)? I think one can find arguments in either direction.

BTW, AMD did do a large chunk of work rebuilding their core for lower area/power consumption with Zen4c. So it must have been worth it for them. Maybe these rumoured 3N EPYC cores are actually Zen5c (and regular Zen5 will be on 4N instead). I think this possibility is at least worth considering.

 

[yellowhelicopter]

M2 is so old at this point

Really? ) People buy computers (or game consoles) to use them for several years at minimum. It's not a phone, and still quite young.

 

[senttoschool]

I don't think that A17 Pro is conservative in any way.

They weren't conservative with new added features but conservative with raw CPU and GPU speed improvements. It could be a Zen2 to Zen3 moment where Zen2 added new features but Zen3 was the chip that allowed AMD to actually lead in performance. Both on 7nm node.

I could see Apple being conservative on number of cores, cache, and other ways of improving raw performance in order to get a smooth 3nm rollout along with new features like ray tracing.