Also, there’s the “problem” that architectures made for the N3B node don’t scale well (?) or are not very compatible (?) with the upcoming N3E process. Yeah, I’m not sure what that means, but I think it points towards a new, much better architecture for the silicon coming with the N3E process, such as the A18 and the A18 Pro chip. And I do expect a big improvement with that generation of silicon.
N3E is
not going to give an inherently better architecture to anyone's design arising from the process itself.
It could be cheaper to make ( not necessarily lower end-user prices). But that is a completely different dimension than performance ( which is where most of this thread it harping on 'better' ). N3E probably results in incrementally bigger dies, but that is offset by the wafer cost being incrementally lower also. Neither of those creates an inherently better implementation architecture.
N3E can push the clocks a bit more because it is not as dense. That too isn't really an arch improvement in and of itself. Pretty likely going to get an architecture of "less stuff' rather than "better stuff" because ran out of transistor budget (and/or die area ) quicker. ( If Apple ports their N3B implementation to N3E likely it is mainly same arch on a slightly bigger die and just some uplift on max clock. Not a much better arch. The single thread drag race folks will cheer , but it is just 'hot rod' of the same stuff. ) .
N3E 'compatible design rule' benefit is that it will be easier to port some architecture implementation to either N3P, N3S , or (extra extremely unlikely in Apple's case) N3X. N3X throw peformance per Watt out the window so
There is hype that lots of folks are going to skip off to TSMC N2 as fast as possible and follow ons to N3E are 'dead'. That is extremely likely not true where end-user package cost is an issue. However, if only going to do 'one' stop on anything N3 variant then N3E doesn't have much over N3B if don't have extremely tight wafer cost constraints.
Wether the M3 chips are based on the A17 Pro (and made using the N3E node) or are they based on the upcoming A18 (and made using the N3E process), is the key, at least for me, to know if this M3 gen is going to be 1) as continuist and iterative as the A17 Pro, just higher clock speeds, more RAM and a more powerful GPU architecture with RayTracing, or 2) they are going to introduce a new e-core, p-core and n-core architecture as well, with higher core counts, which would be a considerable improvement on the Apple Silicon horizon.
A quick shift to N3E for A18 likely just means clock boost of mostly the same stuff on CPU/GPU core front. It would quite easy for Apple just to port the A17 Pro over to N3E and just slap a A18 label on it. And for A18 Pro to just 'bin down' some cores for the A18.
N3P and N3S are going to bring some density improvements that N3E backslided on. But that really is just getting back to N3B like densities. I would be skeptical of major core count increases coming. Maybe more optimized cores for Perf/Watt than the first two, but there is not a ton of extra transistor budget coming at all and the A17 Pro really didn't shrink radically on size even with N3B. ( i.e., Apple has already thrown a lot more 'stuff' onto the die. ) . So pretty likely going to get more specialized cores than a generic "just throw more general purpose cores" approach.
So M5-M6 for general compute core count increases , if any. Core counts is missing forest for the tree.
