M3 Chip Generation - Discussion Megathread

[Boil]

There has always been on-chip memory (core private memory and caches). Dynamic Caching refers to the use of on-core memory by the shaders. It has nothing to do with UMA.

I have always thought the UMA RAM was filling the roles of system memory (CPU) and graphics memory (GPU)...?

So rather than having the GPU cores "locking down" X amount of UMA RAM, the Dynamic Caching allots what is needed as it is needed...?

 

[JPack]

So what happens if you bought a MacBook Pro earlier this month and this happens a few days outside of the return window? Are you basically screwed lol? Asking for a friend…

Return window is 30 days (realistically).

 

[Confused-User]

I clearly paid insufficient attention to the GPU aspects of the A17. Are either the dynamic caching or HW mesh shading features known to exist in the A17? I expected the GPU cores to be identical, or extremely close. Are they?

 

[diamond.g]

I clearly paid insufficient attention to the GPU aspects of the A17. Are either the dynamic caching or HW mesh shading features known to exist in the A17? I expected the GPU cores to be identical, or extremely close. Are they?

Mesh Shading is. I am not sure about the dynamic caching.

 

[Misheemee]

Yeah. I heard that while typing my previous message, but I wasn’t paying enough attention, so I thought “how the hell have they linked the new color with a reduced carbon fingerprint?”

EDIT: Done. 30 minutes of event. New MacBook Pros, and new iMac, with the M3 SoC family.
I’m curious to see if the M3 starts at 8GB or 12GB or RAM

8gb

 

[TigeRick]

Damn Apple, all M3 lineup still using LPDDR5 with reducing memory bus. M3 SoC remains same config, M3 Pro is using 192-bit memory bus. M3 Max is having two type of memory bus support, 30-core GPU is using 384-bit memory bus while 40-core GPU is using 512-bit memory bus. Damn, only Apple can do it.

Memory Density	Memory Size Per Chip x64	128-bit Memory Bus (100GB/s)	192-bit Memory Bus (150GB/s)	384-bit Memory Bus (300GB/s)	512-bit Memory Bus (400GB/S)
	Memory Chips Required	2 pcs	3 pcs	6 pcs (3 chips x 128)	8 pcs (4 chips x 128)
32 Gigabit	4 GB	8 GB
48 Gigabit	6 GB		18 GB	36 GB	48 GB
64 Gigabit	8 GB	16 GB			64 GB
96 Gigabit	12 GB	24 GB	36 GB
128 Gigabit	16 GB			96 GB	128 GB

 

[Confused-User]

Most curious fact in the announcement: the 6P + 6E config for Pro was correct. How utterly bizarre.

It looks like they decided they really need a bigger CPU perf differential between Pro and Max. Not surprising, but it is surprising that they did it this way. Did they actually build a 2P cluster, or is there an entire 4P cluster there with 2P disabled? At their volume, I'd expect the former.

 

[streetfunk]

The CPU numbers are confusing me.
11 core Pro
14 core Studio
is there anywhere a page with the details, P vs. E core numbers ?

Most curious fact in the announcement: the 6P + 6E config for Pro was correct. How utterly bizarre.

It looks like they decided they really need a bigger CPU perf differential between Pro and Max.

completly agree !

 

[neinjohn]

Most curious fact in the announcement: the 6P + 6E config for Pro was correct. How utterly bizarre.

It looks like they decided they really need a bigger CPU perf differential between Pro and Max. Not surprising, but it is surprising that they did it this way. Did they actually build a 2P cluster, or is there an entire 4P cluster there with 2P disabled? At their volume, I'd expect the former.

Wonder how it will benchmark against the M2 Pro. Expect very little on MT and the GPU update is very dependent on the use of new capabilities.

 

[leman]

Most curious fact in the announcement: the 6P + 6E config for Pro was correct. How utterly bizarre.

It looks like they decided they really need a bigger CPU perf differential between Pro and Max. Not surprising, but it is surprising that they did it this way. Did they actually build a 2P cluster, or is there an entire 4P cluster there with 2P disabled? At their volume, I'd expect the former.

Even more, it seems that have more physically different chips. Before it was just Pro and Max, with Pro being a chopped down Max die. Now it looks like we have a Pro (a distinct layout), and two Maxes (shared layout and chopped die). Is N3 so expensive that designing a sets rate die plus additional overhead ends up cheaper?

 

[playtech1]

Most curious fact in the announcement: the 6P + 6E config for Pro was correct. How utterly bizarre.

It looks like they decided they really need a bigger CPU perf differential between Pro and Max. Not surprising, but it is surprising that they did it this way. Did they actually build a 2P cluster, or is there an entire 4P cluster there with 2P disabled? At their volume, I'd expect the former.

I had a go identifying the P Cores from the die shot and I think the M3 Pro does indeed have a design which has 6 P Cores.

Curious that the Pro chip is so distinct from the Max - seems like Apple is getting comfortable with having more than two basic designs and physically cutting them down to segment the lineup.

Hope for a M3 Ultra Pro Max Mac Pro?? (No)

 

[leman]

I have always thought the UMA RAM was filling the roles of system memory (CPU) and graphics memory (GPU)...?

So rather than having the GPU cores "locking down" X amount of UMA RAM, the Dynamic Caching allots what is needed as it is needed...?

UMA is used by both the CPU and the GPU but Dynamic Caching is about assigning on-chip resources to shaders. System memory partitioning has always been dynamic (not to mention that shaders cannot allocate RAM, they can only work with RAM that has been previously allocated by the main application).

 

[smalm]

The accelerators would have no problems supporting my use case. I also doubt that this will change in the future. It's the legacy API that is the problem. If we had SME-like interface to AMX, it would be much more useful in many other domains.

The NPU is more complicated since it can benefit from more specialisation. I am ok with locking it behind APIs.

AMX instructions are private ARM64 instructions. Companies using private ARM64 instructions are not allowed by Arm to expose them. It's part of the architecture licence.

 

[leman]

AMX instructions are private ARM64 instructions. Companies using private ARM64 instructions are not allowed by Arm to expose them. It's part of the architecture licence.

Then they should expose them as streaming SVE with SME. It’s practically the same interface.

 

[sunny5]

Well only 20% from M2 Max to M3 Max which is very disappointing.

 

[Johnny Steps]

Return window is 30 days (realistically).

I thought it was only 14 days based on their terms? Idk, I've never returned something like this to Apple.

 

[JPack]

I thought it was only 14 days based on their terms? Idk, I've never returned something like this to Apple.

On paper, yes. Unless you royally piss off the store clerk, they almost always take it back up to 30 days.

 

[Johnny Steps]

Ah, okay then. Thanks for that. I think I might have to stay with my current MacBook Pro. I'll be exactly one day out of the 30 days for the release date of the new M3 14" MacBook Pro. Plus I'd feel bad scrambling into the Apple Store trying to get this stuff exchanged and probably stress out the person trying to help me.

 

[Rafterman]

On paper, yes. Unless you royally piss off the store clerk, they almost always take it back up to 30 days.

On smaller items maybe. But they will be very resistant to allowing a 30 day return on $3000.

 

[Rafterman]

I don't regret my M2 Max one bit. But that space black does look good.

 

[sunny5]

Damn Apple, all M3 lineup still using LPDDR5 with reducing memory bus. M3 SoC remains same config, M3 Pro is using 192-bit memory bus. M3 Max is having two type of memory bus support, 30-core GPU is using 384-bit memory bus while 40-core GPU is using 512-bit memory bus. Damn, only Apple can do it.

Memory Density	Memory Size Per Chip x64	128-bit Memory Bus (100GB/s)	192-bit Memory Bus (150GB/s)	384-bit Memory Bus (300GB/s)	512-bit Memory Bus (400GB/S)
	Memory Chips Required	2 pcs	3 pcs	6 pcs	8 pcs
32 Gigabit	4 GB	8 GB
48 Gigabit	6 GB		18 GB	36 GB	48 GB
64 Gigabit	8 GB	16 GB			64 GB
96 Gigabit	12 GB	24 GB	36 GB
128 Gigabit	16 GB			96 GB	128 GB

Where is the source?

 

[TigeRick]

Where is the source?

My own research, it is pretty straight forward. You can double check and let me know any mistake

 

[camotwen]

The m3 pro specs are awkward. 18gb ram? 11 cpu cores, and even worse with *5* performance cores?

With 5 vs 6 performance cores I would be surprised if it beats the base m2 pro in raw cpu performance. I will wait to see some tests and reviews before ordering that.

Other than that I would have hoped a 24gb ram option for m3 pro, but well.

 

[JPack]

On smaller items maybe. But they will be very resistant to allowing a 30 day return on $3000.

It depends on how you sell it. I want to return this to get a Dell computer. Nope. I want to return this and get a 4TB model because I’m not satisfied with 1TB. Sure.

I returned my 512GB 15 Pro Max well past 15 days because Costco had $500 off the same thing. A few years ago, I returned MacBook Air at the 30 day mark after M1 came out.

 

[sunny5]

Damn Apple, all M3 lineup still using LPDDR5 with reducing memory bus. M3 SoC remains same config, M3 Pro is using 192-bit memory bus. M3 Max is having two type of memory bus support, 30-core GPU is using 384-bit memory bus while 40-core GPU is using 512-bit memory bus. Damn, only Apple can do it.

Memory Density	Memory Size Per Chip x64	128-bit Memory Bus (100GB/s)	192-bit Memory Bus (150GB/s)	384-bit Memory Bus (300GB/s)	512-bit Memory Bus (400GB/S)
	Memory Chips Required	2 pcs	3 pcs	6 pcs	8 pcs
32 Gigabit	4 GB	8 GB
48 Gigabit	6 GB		18 GB	36 GB	48 GB
64 Gigabit	8 GB	16 GB			64 GB
96 Gigabit	12 GB	24 GB	36 GB
128 Gigabit	16 GB			96 GB	128 GB

How does it affects the performance?